Adapter device for large address spaces

• US 10,255,213 B1
• Filed: 03/28/2016
• Issued: 04/09/2019
• Est. Priority Date: 03/28/2016
• Status: Active Grant

• Current Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Original Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Inventors: Habusha, Adi, Avron, Itai, Gendel, Yaakov
• Primary Examiner(s): Shin, Christopher B
• Application Number:
  US15/083,113
• Time in Patent Office: 1,107 Days
• Field of Search: 710 56
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence

Abstract

Provided are methods and adapter devices for buffering write transactions directed to a large space. In various implementations, an adapter device may include a sequential address buffer and a memory. A region of the memory may be configured as a data block, which may be associated with an address range. The address range may correspond to a region of an address space of a target device. The adapter device may be configured to receive a write transaction, the write transaction having an address and data. The adapter device may further write the address to the sequential address buffer. The adapter device may further determine that the address is within the address range, and to write the data to the data block. The adapter device may further, upon the occurrence of an event, write the data from the data block to the region of the address space of the target device.

Claims

1. An adapter device comprising:

a host interface operable to communicate with a host device;

a target interface operable to communicate with a target device;

a sequential address buffer;

a sequential data buffer; and

a memory, wherein a region of the memory is configured as a data block, wherein the data block is associated with an address range, wherein the address range corresponds to a region of an address space of the target device;

wherein the adapter device is operable to;

receive a first transaction at the host interface, the first transaction having a first address and first data;

write the first address to the sequential address buffer;

determine that the first address is within the address range;

write the first data to the data block;

receive a second transaction at the host interface, the second transaction having a second address and second data;

write the second address to the sequential address buffer;

determine that the second address is outside the address range;

write the second data to the sequential data buffer;

upon occurrence of a first event, write the first data in the data block to the region of the address space using the target interface; and

upon occurrence of a second event, read data from each entry of the sequential data buffer and, using the target interface, write the data read from each entry to the target device.

2. The adapter device of claim 1, wherein the target interface is operable to communicate with the target device using a local storage protocol.

3. The adapter device of claim 1, wherein the target interface is operable to communicate with the target device using a network protocol.

4. An adapter device comprising:

a sequential address buffer;

a sequential data buffer; and

a memory, wherein a region of the memory is configured as a data block, wherein the data block is associated with an address range, wherein the address range corresponds to a region of an address space of a target device;

wherein the adapter device is operable to;

receive a first write transaction, the first write transaction having a first address and first data;

write the first address to the sequential address buffer;

determine that the first address is within the address range;

write the first data to the data block;

upon occurrence of a first event, write the first data from the data block to the region of the address space of the target device;

receive a second write transaction, the second write transaction having a second address and second data;

write the second address to the sequential address buffer;

determine that the second address is outside the address range;

write the second data to the sequential data buffer;

upon occurrence of a second event, read third data from a first entry in the sequential data buffer;

read a third address from a second entry in the sequential address buffer, the second entry corresponding to the first entry; and

write the third data to the target device using the third address.

5. The adapter device of claim 4, wherein the second event comprises determining that an amount of data in the sequential data buffer has reached a threshold.

6. The adapter device of claim 4, wherein the second event comprises determining that a number of addresses in the sequential address buffer that have corresponding data in the sequential data buffer are within a same region of the address space of the target device.

7. The adapter device of claim 4, wherein the first event comprises determining that a pre-determined amount of time has passed.

8. The adapter device of claim 4, wherein the first event comprises determining that the data block contains a pre-determined amount of data.

9. The adapter device of claim 4, wherein the first event comprises:

determining that a number of addresses in the sequential address buffer are within another region of the address space of the target device; and

determining that the number of addresses is above a threshold.

10. The adapter device of claim 4, wherein the adapter device is further operable to modify the address range to correspond to a second region of the address space of the target device.

11. The adapter device of claim 10, wherein the adapter device is further operable to select the second region based on addresses in the sequential address buffer.

12. The adapter device of claim 4, wherein the adapter device is further operable to write information about the first write transaction into the sequential data buffer with the first address.

13. The adapter device of claim 4, wherein the adapter device is configured to examine contents of the sequential address buffer to perform an action, wherein the action includes profiling transactions associated with the contents, monitoring activity associated with the contents, pre-fetching data associated with the contents, or protecting the address space of the target device.

14. The adapter device of claim 4, further comprising:

a translation unit, wherein the translation unit is operable to translate from a host protocol to a network protocol.

15. The adapter device of claim 4, further comprising:

a translation unit, wherein the translation unit is operable to translate from a host protocol to a storage protocol.

16. The adapter device of claim 4, wherein the target device comprises a storage device, a general purpose processor, or a network resource.

17. The adapter device of claim 4, wherein a size of the region of the address space of the target device is less than a size of the address space of the target device.

18. An adapter device, comprising:

a sequential address buffer; and

a sequential data buffer;

wherein the adapter device is operable to communicate with a host device and a target device, and wherein the adapter device is operable to;

receive a write transaction from the host device, the write transaction having an address and data, wherein the write transaction is directed to the target device;

write the address to the sequential address buffer;

write the data to the sequential data buffer; and

upon occurrence of an event;

read first data from a first entry in the sequential data buffer;

read a first address from second entry in the sequential address buffer, wherein the second entry corresponds to the first entry due to the first address being associated with the first data;

write the first data to the target device using the first address;

determine that the first address is within a region of an address space of the target device;

determine that other addresses included in other entries in the sequential address buffer are within the region of the address space of the target device;

extract additional data from entries in the sequential data buffer, wherein the additional data is associated with the other addresses; and

write the additional data to the target device, wherein the first data is written with the additional data.

19. A method comprising:

receiving, at an adapter device, a first write transaction from a host device, the first write transaction having first address and first data, wherein the adapter device includes a sequential address buffer and a memory, wherein a first region of the memory is configured as a sequential data buffer and a second region of the memory is configured as a data block, the data block having an address range, wherein the address range corresponds to a region of memory of a target device;

writing, by the adapter device, the first address to the sequential address buffer;

determining that the first address is within the address range;

writing the first data to the data block;

receiving a second transaction from the host device, the second transaction having a second address and second data;

writing the second address to the sequential address buffer;

determining that the second address is outside the address range;

writing the second data to the sequential data buffer;

upon occurrence of a first event, writing the first data to the region of memory of the target device; and

upon occurrence of a second event, reading data from each entry of the sequential data buffer and writing the data read from each entry to the target device using an address from a corresponding entry in the sequential address buffer.

20. The method of claim 19, wherein the second event comprises determining that an amount of data in the sequential data buffer has reached a threshold.

21. The method of claim 19, wherein the second event comprises determining that a number of addresses in the sequential data buffer that have corresponding data in the sequential data buffer are within a same region of the memory of the target device.

22. The method of claim 19, wherein the first event comprises determining that a pre-determined amount of time has passed.

23. The method of claim 19, wherein the first event comprises determining that the data block contains a pre-determined amount of data.

24. The method of claim 19, wherein the first event comprises:

determining that a number of addresses in the sequential address buffer are within another region of the memory of the target device; and

determining that the number of addresses is above a threshold.