Viewing multi paired schematic and layout windows on printed circuit board (PCB) design software and tools

• US 10,255,401 B2
• Filed: 05/27/2016
• Issued: 04/09/2019
• Est. Priority Date: 04/14/2014
• Status: Active Grant

• Current Assignee: Lenovo Global Technologies International Ltd. (Lenovo Group Ltd.)
• Original Assignee: Lenovo Enterprise Solutions (Singapore) Pte., Ltd. (Lenovo Group Ltd.)
• Inventors: Meng, Jian
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US15/167,864
• Publication Number:
  US 20160275229A1
• Time in Patent Office: 1,047 Days
• Field of Search: 716110-111, 716118-119, 716122
• CPC Class Codes: B60K 2360/741 Instruments adapted for user detection
• CPC Class Codes: B60K 35/65 Instruments specially adapted for specific vehicle types or users, e.g. for left- or right-hand drive
• CPC Class Codes: G06F 21/31 User authentication
• CPC Class Codes: G06F 21/32 using biometric data, e.g. fingerprints, iris scans or voiceprints
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: G06F 2115/12 Printed circuit boards [PCB] or multi-chip modules [MCM]
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H05K 3/0005 for designing circuits by computer

Abstract

A method according to one embodiment includes receiving a printed circuit board design in a memory; generating, using a processor, multiple schematic windows and multiple layout windows of the printed circuit board design; outputting a layout window depicting an entire layout of the printed circuit board design, receiving a user selection of a sub-portion of the printed circuit board design from the entire layout of the printed circuit board design, generating a first of multiple layout windows and a first of multiple schematic windows upon receiving the user selection, and outputting the multiple schematic windows of the printed circuit board design simultaneously with outputting the multiple layout windows of the printed circuit board design. The first of the schematic windows is paired with the first of the layout windows, the paired windows depicting representations of the selected sub-portion of the printed circuit board design.

Claims

1. A method comprising:

receiving a printed circuit board design in a memory;

generating, using a processor, multiple schematic windows of the printed circuit board design;

generating, using the processor, multiple layout windows of the printed circuit board design;

graphically outputting a layout window depicting an entire layout of the printed circuit board design;

receiving, via a user interface, a user selection of a sub-portion of the printed circuit board design from the entire layout of the printed circuit board design;

generating a first of multiple layout windows and a first of multiple schematic windows upon receiving the user selection;

graphically outputting the multiple schematic windows of the printed circuit board design simultaneously with graphically outputting the multiple layout windows of the printed circuit board design,

wherein the first of the schematic windows is paired with the first of the layout windows, the paired windows depicting representations of the selected sub-portion of the printed circuit board design;

receiving, via a user interface, a user selection of a first component of the first of the layout windows; and

outputting a component of the first of the schematic windows corresponding to the selected first component of the paired first of the layout windows in response to receiving the user selection of the first component.

2. The method of claim 1, comprising performing cross-probing between the paired windows.

3. The method of claim 1, comprising performing cross-probing between all of the windows showing a representation of a selected component.

4. The method of claim 1, comprising performing cross-probing between a second of the layout windows and a second of the schematic windows, the second of the layout windows and the second of the schematic windows not being paired windows.

5. The method of claim 1, wherein the windows are simultaneously output to multiple monitors.

6. The method of claim 1, comprising receiving a user selection of a sub-portion of the sub-portion of the printed circuit board design depicted in the first of the layout windows, and generating a second of the layout windows corresponding to the selected sub-portion of the sub-portion.

7. The method of claim 6, comprising generating a second of the schematic windows corresponding to the sub-portion of the sub-portion.

8. The method of claim 1, comprising automatically selecting a second sub-portion of the printed circuit board design connected to the sub-portion of the printed circuit board design depicted in the first of the windows, and generating a second of the layout windows depicting representations of the second sub-portion of the printed circuit board design.

9. A method, comprising:

receiving a printed circuit board design in a memory;

graphically generating, using a processor, multiple schematic windows of the printed circuit board design;

graphically generating, using the processor, multiple layout windows of the printed circuit board design;

graphically outputting the multiple schematic windows of the printed circuit board design simultaneously with graphically outputting the multiple layout windows of the printed circuit board design,

wherein a first of the schematic windows is paired with a first of the layout windows, the paired windows depicting representations of a common sub-portion of the printed circuit board design;

receiving, via a user interface, a user selection of at least a portion of the common sub-portion, and in response thereto, automatically selecting a second sub-portion of the printed circuit board design connected to the common sub-portion of the printed circuit board design depicted in the first of the windows; and

graphically generating a second of the layout windows depicting representations of the second sub-portion of the printed circuit board design.

10. The method of claim 9, comprising performing cross-probing between the paired windows.

11. The method of claim 9, comprising performing cross-probing between all of the windows showing a representation of a selected component.

12. The method of claim 9, comprising performing cross-probing between the second of the layout windows and a second of the schematic windows, the second of the layout windows and the second of the schematic windows not being paired windows.

13. The method of claim 9, wherein the windows are simultaneously output to multiple monitors.

14. The method of claim 9, wherein one of the layout windows depicts an entire layout of the printed circuit board design, and comprising receiving a user selection of the sub-portion of the printed circuit board design from the entire layout of the printed circuit board design, and generating a first of the layout windows and a first of the schematic windows upon receiving the user selection.

15. The method of claim 9, comprising receiving a user selection of a sub-portion of the sub-portion of the printed circuit board design depicted in the first of the layout windows, and generating a second of the layout windows corresponding to the selected sub-portion of the sub-portion.

16. The method of claim 15, comprising generating a second of the schematic windows corresponding to the sub-portion of the sub-portion.

17. A method, comprising:

receiving a printed circuit board design in a memory;

generating, using a processor, multiple schematic windows of the printed circuit board design;

generating, using the processor, multiple layout windows of the printed circuit board design,

graphically outputting the multiple schematic windows of the printed circuit board design simultaneously with graphically outputting the multiple layout windows of the printed circuit board design,

wherein a first of the schematic windows is paired with a first of the layout windows, the paired windows depicting representations of a common sub-portion of the printed circuit board design; and

receiving, via a user interface, a user selection of a sub-portion of the sub-portion of the printed circuit board design depicted in a first of the layout windows, and generating a second of the layout windows corresponding to the selected sub-portion of the sub-portion;

receiving, via a user interface, a user selection of a first component of the first of the schematic windows; and

graphically outputting a component of the first of the layout windows corresponding to the selected first component of the paired first of the schematic windows in response to receiving the user selection of the first component.

18. The method of claim 17, comprising performing cross-probing between all of the windows showing a representation of a selected component.

19. The method of claim 17, comprising performing cross-probing between the second of the layout windows and a second of the schematic windows, the second of the layout windows and the second of the schematic windows not being paired windows.