Method for driving liquid crystal display device

• US 10,255,868 B2
• Filed: 12/18/2017
• Issued: 04/09/2019
• Est. Priority Date: 12/25/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Miyake, Hiroyuki
• Primary Examiner(s): Sharifi-Tafreshi, Koosha
• Application Number:
  US15/844,750
• Publication Number:
  US 20180190219A1
• Time in Patent Office: 477 Days
• Field of Search: 345 87, 345 92
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2300/0404 Matrix technologies
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 2320/10 Special adaptations of display systems for operation with variable images
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

An object is to suppress deterioration of a displayed image even when a refresh rate is reduced in displaying a still image. A liquid crystal display device includes a pixel transistor electrically connected to a pixel electrode, and a capacitor having one electrode electrically connected to the pixel electrode and the other electrode electrically connected to a capacitor line. The pixel transistor is turned on and a voltage based on an image signal is supplied to the pixel electrode, and then, the pixel transistor is turned off so that a holding period during which the pixel electrode holds the voltage based on the image signal starts. A holding signal corresponding to change of the voltage based on the image signal in the pixel electrode in the holding period is supplied to the capacitor line so that a potential of the pixel electrode is constant.

Claims

1. A display device comprising:

a first pixel comprising;

a first transistor;

a first liquid crystal element; and

a first capacitor;

a second pixel comprising;

a second transistor;

a second liquid crystal element; and

a second capacitor; and

a holding signal generation circuit,

wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer comprising a channel formation region,

wherein one of a source and a drain of the first transistor is electrically connected to a pixel electrode of the first liquid crystal element,

wherein a first electrode of the first capacitor is electrically connected to the pixel electrode of the first liquid crystal element,

wherein a second electrode of the first capacitor is electrically connected to a capacitor line,

wherein one of a source and a drain of the second transistor is electrically connected to a pixel electrode of the second liquid crystal element,

wherein a first electrode of the second capacitor is electrically connected to the pixel electrode of the second liquid crystal element,

wherein a second electrode of the second capacitor is electrically connected to the capacitor line,

wherein the holding signal generation circuit is configured to supply a constant voltage to the capacitor line during a moving image display, and

wherein the holding signal generation circuit is configured to supply a holding signal to the capacitor line during a still image display such that a change of a voltage applied to the first liquid crystal element and a change of a voltage applied to the second liquid crystal element are reduced.

2. The display device according to claim 1,

wherein a gate of the first transistor is electrically connected to a gate line, and

wherein a gate of the second transistor is electrically connected to the gate line.

3. The display device according to claim 1,

wherein the other of the source and the drain of the first transistor is electrically connected to a signal line, and

wherein the other of the source and the drain of the second transistor is electrically connected to the signal line.

4. The display device according to claim 1,

wherein a gate of the first transistor is electrically connected to a first gate line,

wherein a gate of the second transistor is electrically connected to a second gate line,

wherein the other of the source and the drain of the first transistor is electrically connected to a first signal line, and

wherein the other of the source and the drain of the second transistor is electrically connected to a second signal line.

5. The display device according to claim 1,

wherein an off-state current of the first transistor is equal to or lower than 1×

10<sup>−

17</sup> A/μ

m.

6. The display device according to claim 1,

wherein the holding signal generation circuit comprises a current source circuit, and

wherein the current source circuit is electrically connected to the second electrode of the first capacitor through the capacitor line.

7. A display device comprising:

a first pixel comprising;

a first transistor;

a first liquid crystal element; and

a first capacitor;

a second pixel comprising;

a second transistor;

a second liquid crystal element; and

a second capacitor; and

a holding signal generation circuit,

wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer comprising a channel formation region,

wherein one of a source and a drain of the first transistor is electrically connected to a pixel electrode of the first liquid crystal element,

wherein a first electrode of the first capacitor is electrically connected to the pixel electrode of the first liquid crystal element,

wherein a second electrode of the first capacitor is electrically connected to a capacitor line,

wherein one of a source and a drain of the second transistor is electrically connected to a pixel electrode of the second liquid crystal element,

wherein a first electrode of the second capacitor is electrically connected to the pixel electrode of the second liquid crystal element,

wherein a second electrode of the second capacitor is electrically connected to the capacitor line,

wherein the holding signal generation circuit is configured to supply a constant voltage to the capacitor line during a first frame period,

wherein the holding signal generation circuit is configured to supply a holding signal to the capacitor line during a second frame period such that a change of a voltage applied to the first liquid crystal element and a change of a voltage applied to the second liquid crystal element are reduced, and

wherein the second frame period is longer than the first frame period.

8. The display device according to claim 7,

wherein a gate of the first transistor is electrically connected to a gate line, and

wherein a gate of the second transistor is electrically connected to the gate line.

9. The display device according to claim 7,

wherein the other of the source and the drain of the first transistor is electrically connected to a signal line, and

wherein the other of the source and the drain of the second transistor is electrically connected to the signal line.

10. The display device according to claim 7,

wherein a gate of the first transistor is electrically connected to a first gate line,

wherein a gate of the second transistor is electrically connected to a second gate line,

wherein the other of the source and the drain of the first transistor is electrically connected to a first signal line, and

wherein the other of the source and the drain of the second transistor is electrically connected to a second signal line.

11. The display device according to claim 7,

wherein an off-state current of the first transistor is equal to or lower than 1×

10<sup>−

17</sup> A/μ

m.

12. The display device according to claim 7,

wherein the holding signal generation circuit comprises a current source circuit, and

wherein the current source circuit is electrically connected to the second electrode of the first capacitor through the capacitor line.