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Semiconductor integrated circuit

  • US 10,255,957 B2
  • Filed: 08/16/2017
  • Issued: 04/09/2019
  • Est. Priority Date: 06/29/2012
  • Status: Active Grant
First Claim
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1. A semiconductor integrated circuit including first and second semiconductor chips that are vertically stacked, the first semiconductor chip comprising:

  • a plurality of column data driving circuit configured to receive a plurality of first column data transmitted in a DDR scheme from the second semiconductor chip, based on an alignment strobe signal, and load the plurality of first column data on a plurality of data input/output lines; and

    an alignment strobe signal driving circuit configured to delay a column strobe signal transmitted from the second semiconductor chip that is source-synchronized with the first column data, by a given delay time, and generate the alignment strobe signal.

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