Semiconductor integrated circuit

• US 10,255,957 B2
• Filed: 08/16/2017
• Issued: 04/09/2019
• Est. Priority Date: 06/29/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Dong-Uk, Kim, Young-Ju, Song, Keun-Soo
• Primary Examiner(s): Le, Vu A
• Application Number:
  US15/678,634
• Publication Number:
  US 20170345471A1
• Time in Patent Office: 601 Days
• Field of Search: 36518905
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/1054 Optical output buffers
• CPC Class Codes: G11C 7/1081 Optical input buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

Claims

1. A semiconductor integrated circuit including first and second semiconductor chips that are vertically stacked, the first semiconductor chip comprising:

a plurality of column data driving circuit configured to receive a plurality of first column data transmitted in a DDR scheme from the second semiconductor chip, based on an alignment strobe signal, and load the plurality of first column data on a plurality of data input/output lines; and

an alignment strobe signal driving circuit configured to delay a column strobe signal transmitted from the second semiconductor chip that is source-synchronized with the first column data, by a given delay time, and generate the alignment strobe signal.

2. The semiconductor integrated circuit of claim 1, wherein the first semiconductor chip receives the first column data in synchronization with a rising edge and a falling edge of the alignment strobe signal.

3. The semiconductor integrated circuit of claim 1, wherein the alignment strobe signal driving circuit comprises:

a column strobe signal input unit configured to receive the column strobe signal based on a column enable signal; and

a delay unit configured to delay the column strobe signal outputted from the column strobe signal input unit, by the given delay time, and output the alignment strobe signal.

4. The semiconductor integrated circuit of claim 3, wherein the alignment strobe signal driving circuit further comprises:

a repeater configured to output the alignment strobe signal with a given driving force.

5. The semiconductor integrated circuit of claim 4, wherein the given delay time corresponds to ¼

cycle of the column strobe signal.

6. The semiconductor integrated circuit of claim 4,

wherein the respective column data are transmitted through at least one first through-chip via that vertically passes through the first semiconductor chip or the second semiconductor chip, and

wherein the column strobe signal is transmitted through a second through-chip via that vertically passes through the first semiconductor chip or the second semiconductor chip.