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Memory array with one shared deep doped region

  • US 10,255,980 B2
  • Filed: 02/26/2018
  • Issued: 04/09/2019
  • Est. Priority Date: 01/19/2016
  • Status: Active Grant
First Claim
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1. A memory array comprising:

  • a plurality of memory pages, each memory page comprising a plurality of memory cells, and each memory cell comprising;

    a floating gate module comprising;

    a floating gate transistor, and configured to control the floating gate transistor according to a source line, a bit line and a word line, the floating gate transistor having a first terminal, a second terminal and a floating gate;

    a source transistor having a first terminal coupled to the source line, a second terminal coupled to the first terminal of the floating gate transistor, and a control terminal coupled to the word line; and

    a bit transistor having a first terminal coupled to the second terminal of the floating gate transistor, a second terminal coupled to the bit line, and a control terminal coupled to the word line;

    a control element having a body terminal coupled to a control line, a first terminal coupled to the body terminal, a second terminal coupled to the body terminal, and a control terminal coupled to the floating gate; and

    an erase element having a body terminal configured to receive a first voltage during a program operation and a program inhibit of the memory cell and receive a second voltage during an erase operation of the memory cell, a first terminal coupled to an erase line, a second terminal coupled to the first terminal of the erase element or being floating, and a control terminal coupled to the floating gate;

    wherein;

    the floating gate module is disposed in a first well;

    the erase element is disposed in a second well;

    the control element is disposed in a third well;

    the first well, the second well and the third well are disposed in a deep doped region;

    memory cells of the plurality of memory pages are all disposed in the deep doped region;

    the control line is at the first voltage during the program operation;

    memory cells in different memory pages are coupled to different control lines, different word lines, and different erase lines;

    during the erase operation of the memory cell;

    the erase line is at the second voltage;

    the control line is at a fifth voltage; and

    the source line and the bit line are both at a fourth voltage or at the fifth voltage;

    while the word line is at the fourth voltage or at the fifth voltage;

    the second voltage is greater than the fourth voltage, and the fourth voltage is greater than the fifth voltage; and

    a difference between the fourth voltage and the fifth voltage is smaller than half of a difference between the second voltage and the fifth voltage.

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