Accidental fuse programming protection circuits

• US 10,255,982 B2
• Filed: 10/31/2017
• Issued: 04/09/2019
• Est. Priority Date: 11/02/2016
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Zhou, Bo, Blin, Guillaume Alexandre
• Primary Examiner(s): Bui, Tha-O H
• Application Number:
  US15/798,739
• Publication Number:
  US 20180151240A1
• Time in Patent Office: 525 Days
• Field of Search: 365 96
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48229 the bond pad protruding from the surface of the item
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/1205 Capacitor
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1427 Voltage regulator [VR]
• CPC Class Codes: H01L 2924/1431 Logic devices
• CPC Class Codes: H01L 2924/145 Read-only memory [ROM]
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

Apparatus and methods for protection against inadvertent programming of fuse cells are provided herein. In certain configurations, a fuse system includes a fuse programming transistor, a cascode transistor, and a fuse cell electrically connected in series between a first pad and a second pad. The fuse system further includes a bias generator that controls an amount of current provided to the fuse cell based on biasing a gate of the fuse programming transistor and a gate of the cascode transistor. The fuse system further includes a fuse protection capacitor electrically connected between the first pad and the gate of the cascode transistor to prevent inadvertent programming of the fuse cell in response to an increase in voltage of the first pad relative to the second pad.

Claims

1. A fuse system for a semiconductor die, the fuse system comprising:

a plurality of pads including a first pad and a second pad;

a plurality of switches including a first switch and a second switch;

a fuse electrically connected in series with the first switch and the second switch between the first pad and the second pad;

a biasing circuit configured to bias a control input of the first switch with a fuse programming signal to thereby control a current through the fuse; and

a fuse protection capacitor electrically connected between the first pad and a control input of the second switch, the fuse protection capacitor operable to inhibit unintended programming of the fuse by adjusting a bias of the second switch in response to a change in a voltage of the first pad relative to a voltage of the second pad.

2. The fuse system of claim 1 wherein the biasing circuit includes a voltage regulator electrically connected between the first pad and the second pad and configured to generate a regulated voltage, and a programming logic circuit configured to generate the fuse programming signal based on the regulated voltage.

3. The fuse system of claim 2 wherein the voltage regulator is further configured to bias the control input of the second switch, the fuse protection capacitor operable to prevent accidental programming of the fuse arising from a delay of the voltage regulator in providing voltage regulation.

4. The fuse system of claim 3 wherein the voltage regulator is a low dropout regulator.

5. The fuse system of claim 2 wherein the programming logic circuit includes a level shifter configured to generate the fuse programming signal by level shifting a control signal, the level shifter configured to control the fuse programming signal to a first voltage level about equal to the voltage of the first pad in a first state of the control signal, and to control the fuse programming signal to a second voltage level about equal to the regulated voltage in a second state of the control signal.

6. The fuse system of claim 2 further comprising a serial interface configured to provide a control signal to the programming logic circuit to instruct programming of the fuse.

7. The fuse system of claim 1 wherein the first switch is implemented as a fuse programming field-effect transistor, and the second switch is implemented as a cascode field-effect transistor.

8. The fuse system of claim 1 wherein the first pad is a shared power supply and fuse programming pad and the second pad is a ground pad.

9. The fuse system of claim 1 further comprising a fuse sensing circuit electrically connected to the fuse and configured to detect a state of the fuse.

10. The fuse system of claim 1 wherein the biasing circuit is further configured to bias the control input to the second switch based on a voltage difference between the first pad and the second pad.

11. A method of protecting from accidental fuse programming, the method comprising:

biasing a control input of a first switch with a fuse programming signal;

controlling a current through the fuse based on the fuse programming signal, the fuse electrically connected in series with the first switch and a second switch between a first pad and a second pad; and

inhibiting unintended programming of the fuse by adjusting a bias of the second switch using a fuse protection capacitor in response to a change in a voltage of the first pad relative to a voltage of the second pad, the fuse protection capacitor electrically connected between the first pad and a control input of the second switch.

12. The method of claim 11 further comprising biasing the control input of the second switch based on a voltage difference between the first pad and the second pad.

13. The method of claim 11 further comprising generating a regulated voltage using a voltage regulator that is electrically connected between the first pad and the second pad, and generating the fuse programming signal based on the regulated voltage.

14. The method of claim 13 further comprising biasing the control input of the second switch using the voltage regulator, and preventing accidental programming of the fuse arising from a delay of the voltage regulator in providing voltage regulation.

15. A packaged module comprising:

a package substrate; and

a semiconductor die attached to the package substrate, the semiconductor die including a first switch, a second switch, and a fuse electrically connected in series with one another between a first pad and a second pad, the semiconductor die further including a biasing circuit configured to bias a control input of the first switch with a fuse programming signal to thereby control a current through the fuse, and a fuse protection capacitor electrically connected between the first pad and a control input of the second switch, the fuse protection capacitor operable to inhibit unintended programming of the fuse by adjusting a bias of the second switch in response to a change in a voltage of the first pad relative to a voltage of the second pad.

16. The packaged module of claim 15 wherein the biasing circuit includes a voltage regulator electrically connected between the first pad and the second pad and configured to generate a regulated voltage, and a programming logic circuit configured to generate the fuse programming signal based on the regulated voltage.

17. The packaged module of claim 16 wherein the voltage regulator is further configured to bias the control input of the second switch, the fuse protection capacitor operable to prevent accidental programming of the fuse arising from a delay of the voltage regulator in providing voltage regulation.

18. The packaged module of claim 16 wherein the programming logic circuit includes a level shifter configured to generate the fuse programming signal by level shifting a control signal, the level shifter configured to control the fuse programming signal to a first voltage level about equal to the voltage of the first pad in a first state of the control signal, and to control the fuse programming signal to a second voltage level about equal to the regulated voltage in a second state of the control signal.

19. The packaged module of claim 15 wherein the first pad is a shared power supply and fuse programming pad and the second pad is a ground pad, the semiconductor die further including a core circuit configured to receive power from the first pad and the second pad.

20. The packaged module of claim 15 wherein the biasing circuit is further configured to bias the control input to the second switch based on a voltage difference between the first pad and the second pad.