Self-aligned trench isolation in integrated circuits

• US 10,256,137 B2
• Filed: 11/03/2017
• Issued: 04/09/2019
• Est. Priority Date: 10/08/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Lu, Ching-Huang, Xue, Lei, Ohtsuka, Kenichi, Chan, Simon Siu-Sing, Sugino, Rinji
• Primary Examiner(s): Sarkar, Asok K
• Assistant Examiner(s): Withers, Grant S
• Application Number:
  US15/802,721
• Publication Number:
  US 20180166323A1
• Time in Patent Office: 522 Days
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

An A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

Claims

1. A method, comprising:

forming first and second partial gate structures adjacent one another over a substrate, wherein a defined area in the substrate is located between the first and second partial gate structures;

wherein the first and second partial gate structures have a partial gate layer that has a smaller vertical dimension than a complete gate layer;

forming a self-aligned trench in the defined area between the first and second partial gate structures;

filling a first portion of the self-aligned trench with a dielectric material;

filling a second portion of the self-aligned trench with a conductive material; and

after filling the first and second portions of the self-aligned trench, forming an additional gate layer over the partial gate layer of the first and second partial gate structures to form gate structures with the complete gate layer.

2. The method of claim 1, wherein forming the first and second partial gate structures comprises forming a dielectric layer over the substrate and forming a partial gate layer over the dielectric layer.

3. The method of claim 1, further comprising forming first and second doped regions for the first and second partial gate structures, wherein the first and second doped regions are substantially in contact with at least a part of the second filled portion of the self-aligned trench.