Semiconductor device with slotted backside metal for improving Q factor

• US 10,256,187 B2
• Filed: 05/15/2017
• Issued: 04/09/2019
• Est. Priority Date: 05/15/2017
• Status: Active Grant

• Current Assignee: Win Semiconductors Corporation
• Original Assignee: Win Semiconductors Corporation
• Inventors: Chiu, Jui-Chieh, Huang, Chih-Wen, Lai, You-Cheng
• Primary Examiner(s): Abdelaziez, Yasser A
• Application Number:
  US15/594,672
• Publication Number:
  US 20180331031A1
• Time in Patent Office: 694 Days
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/00 Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 28/10 Inductors

Abstract

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a winding structure formed on a top side the semiconductor substrate, wherein the winding structure comprises one or more metal lines winding with respect to a center of the winding structure; and a backside metal formed under a backside of the semiconductor substrate; wherein a hollow slot is formed within the backside metal, and a projection of the winding structure is within the hollow slot.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a winding structure formed on a top side the semiconductor substrate, wherein the winding structure comprises one or more metal lines winding with respect to a center of the winding structure; and

a first backside metal and a second backside metal formed under a backside of the semiconductor substrate;

wherein a hollow slot is formed between the first backside metal and the second backside metal, and a projection of the winding structure is within the hollow slot;

wherein the first backside metal and the second backside metal forms a ground-signal-ground (GSG) structure;

wherein an edge of the hollow slot is a distance from a projection result of an outmost metal line of the winding structure.

2. The semiconductor device of claim 1, wherein the semiconductor substrate is made of Gallium Arsenide (GaAs) or Silicon Carbide (SiC).

3. The semiconductor device of claim 1, further comprising:

a dielectric layer formed on the semiconductor substrate;

wherein the winding structure is formed within the dielectric layer.

4. The semiconductor device of claim 3, wherein the one or more metal lines are disposed in multiple metal layers, and one or more first vias are formed within the dielectric layer to connect the one or more metal lines disposed in the multiple metal layers.

5. The semiconductor device of claim 1, wherein a high electron mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT) is formed on the semiconductor substrate.

6. The semiconductor device of claim 1, wherein the winding structure is an inductor.

7. The semiconductor device of claim 1, wherein the winding structure is a transformer.

8. The semiconductor device of claim 1, wherein the winding structure is a balun.

9. The semiconductor device of claim 1, further comprising:

a topside metal formed on the top side the semiconductor substrate;

wherein a second via is formed within the semiconductor substrate to connect the topside metal with the backside metal.

10. The semiconductor device of claim 1, wherein a part of the backside metal is for providing grounding for the semiconductor device.

11. The semiconductor device of claim 10, wherein an area of the part of the backside metal for providing grounding is larger than 50% of an area of the backside of the semiconductor device.

12. The semiconductor device of claim 1, wherein a part of the backside metal is for delivering radio frequency (RF) signal or DC bias of the semiconductor device.

13. The semiconductor device of claim 12, wherein an area of the part of the backside metal for delivering RF signal is smaller than 50% of an area of the backside of the semiconductor device.

14. The semiconductor device of claim 1, wherein an area of the hollow slot is smaller than 30% of an area of the backside of the semiconductor device.

17. The semiconductor device of claim 9, wherein a distance between an edge of the backside metal and an edge of the second via is at least 30 um.

18. The semiconductor device of claim 1, wherein the GSG structure is formed at an edge of the semiconductor device.

19. The semiconductor device of claim 1, wherein the hollow slot has a same width at an edge of semiconductor device.

15. A manufacturing method of a semiconductor device, comprising:

forming a winding structure formed on a top side of a semiconductor substrate, wherein the winding structure comprises one or more metal lines winding with respect to a center of the winding structure, and the one or more metal lines are disposed in one or more metal layers;

forming a first backside metal and a second backside metal under a backside of the semiconductor substrate; and

forming a hollow slot between the first backside metal and the second backside metal, wherein a projection area of the winding structure is within the hollow slot, and an edge of the hollow slot is a distance from a projection result of an outmost metal line of the winding structure;

wherein the first backside metal and the second backside metal forms a ground-signal-ground (GSG) structure.

16. The manufacturing method of claim 15, wherein the hollow slot is formed by a hot-via-forming process within the backside metal.