Forming embedded circuit elements in semiconductor package assembles and structures formed thereby

• US 10,256,219 B2
• Filed: 09/08/2016
• Issued: 04/09/2019
• Est. Priority Date: 09/08/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chew, Yen Hsiang
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US15/260,138
• Publication Number:
  US 20180068989A1
• Time in Patent Office: 943 Days
• Field of Search: 257686, 257777, 257778, 257528
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/0569 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13298 Fillers
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73209 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73217 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/165 : Containers
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

Methods of forming stacked die assemblies are described. Those methods/structures may include forming a circuit element on a first substrate, wherein a first die is adjacent the circuit element, forming a via disposed directly on a surface of the circuit element, and forming a mold compound on the first die, on the circuit element and on the via, wherein the via and circuit element are completely embedded within the mold compound. A routing layer is formed on a top surface of the mold compound, and a second die is coupled with the routing layer.

Claims

1. A microelectronic package structure comprising:

a first package comprising;

a first die on a first substrate;

a first circuit element on the first substrate and adjacent a first side of the first die, wherein a first contact structure is on a sidewall surface of the first circuit element;

a second circuit element on the first substrate and adjacent a second side, opposite the first side of the die, wherein a second contact structure is on a sidewall surface of the second circuit element;

a mold material over the first die and directly on at least a portion of the top surface of the first circuit element and on at least a portion of the top surface of the second circuit element;

a first embedded via structure directly on a top surface of the first contact structure, and a second embedded via structure directly on a top surface of the second contact structure, wherein the first embedded via structure and the second embedded via structure extend through the mold material, wherein the first and the second embedded via structures comprise a conductive material;

a routing layer, wherein the routing layer comprises a single, continuous conductive layer, directly on a top surface of the first embedded via structure and directly on a top surface of the second embedded via structure, wherein the routing layer extends between the first and second embedded via structures; and

a second package over the first package, the second package comprising;

a second die over the first die.

2. The microelectronic package structure of claim 1 wherein the top surfaces of the first embedded via structure and the second embedded via structure are coplanar with a top surface of the mold material, and wherein the first and second embedded via structures extends above a surface of the first die, wherein the surface of the first die is opposite a top surface of the first substrate.

3. The microelectronic package structure of claim 2 wherein the routing layer comprises copper, and extends continuously over the entire surface of the first die.

4. The microelectronic package structure of claim 1 wherein at least one of the first circuit element or the second circuit element comprises one of a resistor, a capacitor or an inductor.

5. The microelectronic package structure of claim 2 wherein a third contact structure is on an opposite sidewall surface of the first circuit element, and a third embedded via structure is on a top surface of the third contact structure, wherein the mold material is between the first embedded via structure and the third embedded via structure.

6. The microelectronic package structure of claim 1 wherein at least one of the first or second circuit elements is electrically coupled to only one of the first package or the second package.

7. The microelectronic package structure of claim 1 wherein at least one of the first or second circuit elements is electrically coupled to both the first package and the second package.

8. The microelectronic package structure of claim 1 wherein the mold material comprises a heat conductive and an electrically insulating mold compound.

9. A microelectronic package structure comprising:

a first package comprising;

a first die on a first substrate;

a first circuit element adjacent a first side of the first die and on the first substrate;

a second circuit element on the first substrate and adjacent a second side, opposite the first side of the die;

a first embedded via structure on at least a portion of a top surface of the first circuit element, wherein the first embedded via structure comprises a conductive material;

a second embedded via structure on at least a portion of a top surface of the second circuit element, wherein the second embedded via structure comprises a conductive material;

a mold material directly on a top surface of the first die, wherein the mold material is further directly on at least a portion of the top surfaces of the first and second circuit elements, and is directly on the first and second embedded via structures;

a routing layer, wherein the routing layer comprises a single, continuous conductive layer, directly on a top surface of the first embedded via structure and directly on a top surface of the second embedded via structure, wherein the routing layer extends between the first and second embedded via structures;

a second package over the first package comprising;

a second die over the first die.

10. The microelectronic package structure of claim 9 wherein the routing layer is on the entire top surface of the mold compound.

11. The microelectronic package structure of claim 9 wherein the first and second embedded via structures are entirely embedded within the mold compound.

12. The microelectronic package structure of claim 9 wherein at least one of the first or the second circuit element is a resistor, a capacitor or an inductor.

13. The microelectronic package structure of claim 9 wherein at least one of the first or the second embedded via structures is electrically coupled to conductive structures in the first substrate.

14. The microelectronic package structure of claim 9 wherein the first die comprises a microprocessor, and the second die comprises a portion of a wearable device.

15. The microelectronic package structure of claim 9 wherein the second die comprises an RF die.

16. The device structure of claim 9, wherein the second die is bonded to the routing layer.