Method for integrating a light emitting device

• US 10,256,221 B2
• Filed: 12/21/2017
• Issued: 04/09/2019
• Est. Priority Date: 06/17/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Bibl, Andreas, Griggs, Charles R.
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US15/850,862
• Publication Number:
  US 20180182746A1
• Time in Patent Office: 474 Days
• Field of Search: None
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2933/0025 relating to coatings
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 2933/005 relating to encapsulations
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0008 having p-n or hi-lo junctions
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/30 : containing only elements of Group III and Group V of the Periodic Table
• CPC Class Codes: H01L 33/44 : characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/52 : Encapsulations
• CPC Class Codes: H01L 33/54 : having a particular shape
• CPC Class Codes: H01L 33/56 : Materials, e.g. epoxy or silicone resin
• CPC Class Codes: H01L 33/60 : Reflective elements
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the bank layer and laterally around the micro LED device within the reflective bank structure. A portion of the micro LED device and a conductive line atop the bank layer protrude above a top surface of the passivation layer.

Claims

1. A display panel comprising:

a substrate;

a plurality of light emitting diode (LEDs) on the substrate and within a pixel area of the display panel;

a plurality of Vss tie lines in the substrate and extending across the pixel area of the display panel;

wherein the substrate further comprises a planarization layer over the plurality of Vss tie lines, and the LEDs are over the planarization layer;

a patterned dam layer over the planarization layer;

a metal layer on top of the patterned dam layer, wherein the metal layer is in electrical contact with the plurality of Vss tie lines; and

one or more top conductive electrode layers that electrically connect the plurality of LEDs with the plurality of Vss tie lines.

2. The display panel of claim 1, wherein the plurality of Vss tie lines run in a row-wise direction across the pixel area.

3. The display panel of claim 1, wherein the plurality of Vss tie lines run in a column-wise direction across the pixel area.

4. The display panel of claim 1, wherein the plurality of Vss tie lines run in both a row-wise direction and column-wise direction across the pixel area.

5. The display panel of claim 1, wherein the plurality of Vss tie lines are coupled to a flexible circuit board (FCB).

6. The display panel of claim 1, further comprising a passivation layer over the substrate and laterally around the plurality of LEDs.

7. The display panel of claim 6, wherein the one or more top conductive electrode layers are over the passivation layer.

8. The display panel of claim 7, wherein the plurality of Vss tie lines run in a row-wise direction across the pixel area.

9. The display panel of claim 7, wherein the plurality of Vss tie lines run in a column-wise direction across the pixel area.

10. The display panel of claim 7, wherein the plurality of Vss tie lines run in both a row-wise direction and column-wise direction across the pixel area.

11. The display panel of claim 1, wherein the one or more top conductive electrodes are in direct contact with the metal layer on top of the patterned dam layer.

12. The display panel of claim 1, the metal layer comprises a plurality of via contacts electrically connected to the plurality of Vss tie lines.

13. The display panel of claim 1, further comprising:

a passivation layer over the substrate and laterally around the plurality of LEDs, wherein the one or more top conductive electrode layers are over the passivation layer; and

a plurality of recesses in a top surface of the passivation layer to expose the plurality of LEDs, wherein the one or more top conductive electrodes contact the plurality of LEDs in the plurality of recesses.

14. The display panel of claim 13, wherein the passivation layer comprises a thermoset material.

15. The display panel of claim 14, wherein the thermoset material is an acrylic.

16. The display panel of claim 13, wherein each LED comprises a vertical p-n diode between a bottom contact and a top contact.