Cells having transistors and interconnects including nanowires or 2D material strips

• US 10,256,223 B2
• Filed: 07/22/2016
• Issued: 04/09/2019
• Est. Priority Date: 06/23/2014
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Kawa, Jamil, Moroz, Victor
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US15/217,252
• Publication Number:
  US 20160329313A1
• Time in Patent Office: 991 Days
• Field of Search: 716119
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G06F 2111/14 related to nanotechnology
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a plurality of transistors and an interconnect; wherein a transistor in the plurality has a channel comprising one or more nanowires or 2D material strips arranged in parallel, and the interconnect comprises one or more nanowires or 2D material strips arranged in parallel and connected to terminals of more than one of the transistors in the plurality of transistors. An integrated circuit including the plurality of transistors and the interconnect is described.

Claims

1. A computer system adapted to process a computer implemented representation of a circuit design, comprising:

a processor and memory coupled to the processor, the memory storing instructions executable by the processor, including instructions to select cells from a cell library;

the cell library including entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language; and

at least one entry in the cell library comprising a specification of physical structures and timing parameters of a NAND gate including;

a plurality of transistors, at least one transistor in the plurality of transistors comprising a channel including nanowires or 2D material strips; and

a plurality of interconnects configured to connect terminals of the transistors.

2. The computer system of claim 1, wherein at least one interconnect in the plurality of interconnects comprising other nanowires or 2D material strips.

3. The computer system of claim 1, wherein the nanowires or 2D material strips in the channel are disposed vertically.

4. The computer system of claim 1, wherein the other nanowires or 2D material strips in the interconnect are disposed vertically.

5. The computer system of claim 1, the NAND gate comprising:

a first transistor in the plurality of transistors having a first channel, and connected in parallel between first and second terminals, the second terminal connected to an output of the logic cell;

a second transistor in the plurality of transistors having a second channel, and connected in parallel between third and fourth terminals, the fourth terminal connected to the output of the logic cell;

a third transistor in the plurality of transistors having a third channel, and connected in parallel between fifth and sixth terminals, the sixth terminal connected to the output of the logic cell;

a fourth transistor in the plurality of transistors having a fourth channel, and connected in parallel between seventh and eighth terminals;

a first gate conductor crossing the first channel of the first transistor between the first and second terminals and crossing a third channel of the third transistor between the fifth and sixth terminals;

a second gate conductor crossing the second channel of the second transistor between the third and fourth terminals and crossing the fourth channel of the fourth transistor between the seventh and eighth terminals;

a first source region, a second source region, a third source region and a fourth source region connected to the first terminal, third terminal, fifth terminal and seventh terminal, respectively;

a first interconnect in the plurality of interconnects connecting a first power conductor to the first source region;

a second interconnect in the plurality of interconnects connecting the first power conductor to the second source region;

a third interconnect in the plurality of interconnects connecting the eighth terminal of the fourth transistor to the third source region; and

a fourth interconnect in the plurality of interconnects connecting a second power conductor to the seventh terminal of the fourth transistor.

6. The computer system of claim 5, wherein at least one of the first source region, the second source region, the third source region and the fourth source region includes a set of nanowires or 2D material strips disposed horizontally and connected in parallel.

7. A computer program product, comprising:

a memory including non-transitory computer-readable media having stored thereon a cell library including entries for a plurality of cells, entries in the cell library including a machine readable specification of a cell, the specification of the cell including computer readable parameters specifying structural features of a physical implementation of a NAND gate, the specification of the cell being executable by a computer using the computer readable parameters stored on the non-transitory computer-readable media to run a placement process to control physical placement of the NAND gate with other circuits or components, the NAND gate including;

a plurality of transistors, at least one transistor in the plurality of transistors comprising a channel including nanowires or 2D material strips; and

a plurality of interconnects configured to connect terminals of the transistors.

8. The computer program product of claim 7, wherein at least one interconnect in the plurality of interconnects comprising other nanowires or 2D material strips.

9. The computer program product of claim 7, wherein the nanowires or 2D material strips in the channel are disposed vertically.

10. The computer program product of claim 7, wherein the other nanowires or 2D material strips in the interconnect are disposed vertically.

11. The computer program product of claim 7, the NAND gate comprising:

a first transistor in the plurality of transistors having a first channel, and connected in parallel between first and second terminals, the second terminal connected to an output of the logic cell;

a second transistor in the plurality of transistors having a second channel, and connected in parallel between third and fourth terminals, the fourth terminal connected to the output of the logic cell;

a third transistor in the plurality of transistors having a third channel, and connected in parallel between fifth and sixth terminals, the sixth terminal connected to the output of the logic cell;

a fourth transistor in the plurality of transistors having a fourth channel, and connected in parallel between seventh and eighth terminals;

a first gate conductor crossing the first channel of the first transistor between the first and second terminals and crossing a third channel of the third transistor between the fifth and sixth terminals;

a second gate conductor crossing the second channel of the second transistor between the third and fourth terminals and crossing the fourth channel of the fourth transistor between the seventh and eighth terminals;

a first source region, a second source region, a third source region and a fourth source region connected to the first terminal, third terminal, fifth terminal and seventh terminal, respectively;

a first interconnect in the plurality of interconnects connecting a first power conductor to the first source region;

a second interconnect in the plurality of interconnects connecting the first power conductor to the second source region;

a third interconnect in the plurality of interconnects connecting the eighth terminal of the fourth transistor to the third source region; and

a fourth interconnect in the plurality of interconnects connecting a second power conductor to the seventh terminal of the fourth transistor.

12. The computer program product of claim 11, wherein at least one of the first source region, the second source region, the third source region and the fourth source region includes a set of nanowires or 2D material strips disposed horizontally and connected in parallel.

13. A circuit, comprising a NAND gate including:

a plurality of transistors, at least one transistor in the plurality of transistors comprising a channel including nanowires or 2D material strips; and

a plurality of interconnects configured to connect terminals of the transistors.

14. The circuit of claim 13, wherein at least one interconnect in the plurality of interconnects comprising other nanowires or 2D material strips.

15. The circuit of claim 13, wherein the nanowires or 2D material strips in the channel are disposed vertically.

16. The circuit of claim 13, wherein the other nanowires or 2D material strips in the interconnect are disposed vertically.

17. The circuit of claim 13, the NAND gate comprising:

a first transistor in the plurality of transistors having a first channel, and connected in parallel between first and second terminals, the second terminal connected to an output of the logic cell;

a second transistor in the plurality of transistors having a second channel, and connected in parallel between third and fourth terminals, the fourth terminal connected to the output of the logic cell;

a third transistor in the plurality of transistors having a third channel, and connected in parallel between fifth and sixth terminals, the sixth terminal connected to the output of the logic cell;

a fourth transistor in the plurality of transistors having a fourth channel, and connected in parallel between seventh and eighth terminals;

a first gate conductor crossing the first channel of the first transistor between the first and second terminals and crossing a third channel of the third transistor between the fifth and sixth terminals;

a second gate conductor crossing the second channel of the second transistor between the third and fourth terminals and crossing the fourth channel of the fourth transistor between the seventh and eighth terminals;

a first source region, a second source region, a third source region and a fourth source region connected to the first terminal, third terminal, fifth terminal and seventh terminal, respectively;

a first interconnect in the plurality of interconnects connecting a first power conductor to the first source region;

a second interconnect in the plurality of interconnects connecting the first power conductor to the second source region;

a third interconnect in the plurality of interconnects connecting the eighth terminal of the fourth transistor to the third source region; and

a fourth interconnect in the plurality of interconnects connecting a second power conductor to the seventh terminal of the fourth transistor.

18. The circuit of claim 17, wherein at least one of the first source region, the second source region, the third source region and the fourth source region includes a set of nanowires or 2D material strips disposed horizontally and connected in parallel.