Forming switch circuit with controllable phase node ringing

• US 10,256,236 B2
• Filed: 08/02/2018
• Issued: 04/09/2019
• Est. Priority Date: 10/14/2016
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Pan, Ji, Lui, Sik
• Primary Examiner(s): Menz, Laura M
• Application Number:
  US16/053,607
• Publication Number:
  US 20180342506A1
• Time in Patent Office: 250 Days
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal of the switch circuit, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off. The first MOS transistor is characterized by a first reverse gate-to-drain capacitance (C_rss) and the second MOS transistor is characterized by a second C_rss that is greater than the first C_rss.

Claims

1. A method for forming a switch circuit, comprising:

forming an array of trench transistor cells in a semiconductor layer of a first conductivity type, the trench transistor cells being defined by trench gate structures, each of said gate trench structures including a trench formed in the semiconductor layer and an insulated gate electrode formed in the trench;

forming first body regions of a second conductivity type that is opposite the first conductivity type in a first subset of the trench transistor cells, the first body regions and trenches of the first subset of the trench transistor cells being characterized by a first distance from a bottom of the first body regions to a bottom of the gate trenches in the first subset associated with a first reverse gate-to-drain capacitance (C_rss);

forming second body regions of the second conductivity type that is opposite the first conductivity type in a second subset of the trench transistor cells, the second body regions and trenches of the second subset of the trench transistor cells being characterized by a second distance from a bottom of the second body regions to a bottom of the gate trenches in the second subset associated with a second reverse gate-to-drain capacitance (C_rss), wherein the second distance is greater than the first distance; and

forming source regions in the array of trench transistor cells.

2. The method of claim 1, wherein forming the array of trench transistor cells includes forming the gate trenches in the second subset so that a depth of the bottom of the gate trenches in the second subset is greater than a depth than of the bottom of the gate trenches in the first subset and wherein forming the first and second body regions includes forming the first body regions so that the bottom of the first body regions is the same depth as the bottom of the second body regions.

3. method of claim 2, wherein forming the gate trenches in the second subset so that a depth of the bottom of the gate trenches in the second subset is greater than a depth than of the bottom of the gate trenches in the first subset includes etching trenches in the first and second subsets to a first depth, protecting the trenches in the first subset with a mask while leaving the trenches in the second subset unmasked, and etching the trenches in the second subset to a second depth that is deeper than the first depth.

4. The method of claim 2, wherein forming the gate trenches in the second subset so that a depth of the bottom of the gate trenches in the second subset is greater than a depth than of the bottom of the gate trenches in the first subset includes etching trenches in the second subsets to a specific depth using a first trench mask, then applying a second trench mask to etch the trenches in the first subset with a mask while leaving the trenches in the second subset unmasked, and etching the trenches in the second subset to a second depth that is deeper than the first depth.

5. The method of claim 1, wherein forming the array of trench transistor cells includes forming the gate trenches in the first and second subsets to a common depth of the bottom of the gate trenches in the first and second subsets and wherein forming the first and second body regions includes forming the first body regions so that the bottom of the second body regions is the greater depth than the bottom of the first body regions.

6. The method of claim 5, wherein forming the first body regions so that the bottom of the second body regions is the greater depth than the bottom of the first body regions includes forming the first and second body regions to a first depth using a first implant process at a first implant energy, protecting the second body regions from a second implant with a mask while leaving the first body regions unmasked, and performing a second implant in the first body regions at a second energy that is greater than the first energy.

7. The method of claim 1, wherein forming the array of trench transistor cells includes forming the gate trenches in the second subset so that a depth of the bottom of the gate trenches in the second subset is greater than a depth than of the bottom of the gate trenches in the first subset and wherein forming the first and second body regions includes forming the first body regions so that the bottom of the second body regions is the greater depth than the bottom of the first body regions.

8. The method of claim 1, wherein the first subset of transistor cells forms a first MOS transistor and wherein the second subset of transistor cells forms a second MOS transistor.

9. The method of claim 8, wherein a transistor area of the second MOS transistor is between 0.1% and 15% of a total area of the common active device area.

10. The method of claim 8, wherein the first MOS transistor is a first NMOS transistor and the second MOS transistor is a second NMOS transistor.

11. The method of claim 10, wherein each of the first NMOS transistor and the second NMOS transistor comprises one or more trench transistors, each of the one or more trench transistors having a gate terminal formed in a trench in an N-type semiconductor layer on the common N-type semiconductor substrate, a P-type body region formed in the semiconductor layer and an N-type source region formed proximate the trench.