High doped III-V source/drain junctions for field effect transistors

• US 10,256,304 B2
• Filed: 02/07/2018
• Issued: 04/09/2019
• Est. Priority Date: 07/29/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Cai, Xiuyu, Liu, Qing, Wang, Kejia, Xie, Ruilong, Yeh, Chun-Chen
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US15/890,880
• Publication Number:
  US 20180175202A1
• Time in Patent Office: 426 Days
• CPC Class Codes: H01L 21/30621 Vapour phase etching
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e¹⁸ to about 1e²⁰ atoms/cm³ and contacting the epitaxial contacts.

Claims

1. A semiconductor device, comprising:

a gate arranged on a substrate;

a pair of epitaxial contacts comprising a III-V material arranged on opposing sides of the gate;

a channel region arranged underneath the gate and between the pair of epitaxial contacts, the channel region comprising a discrete undoped III-V material region between doped III V material regions; and

a buffer layer between the channel region and the substrate, the buffer layer comprising copper doped silicon.

2. The semiconductor device of claim 1, wherein the doped III-V material regions comprise an n-type dopant.

3. The semiconductor device of claim 1, wherein the doped III-V material regions comprise a p-type dopant.

4. The semiconductor device of claim 1, wherein the III-V material of the pair of epitaxial contacts is doped.

5. The semiconductor device of claim 4, wherein the III-V material of the pair of epitaxial contacts is the same as the doped III-V material regions under the gate.

6. The semiconductor device of claim 1, wherein the gate further comprises spacers along sidewalls of the gate.

7. The semiconductor device of claim 6, wherein the doped III-V material regions are positioned under the gate between the spacers and the substrate.

8. The semiconductor device of claim 6, wherein the doped III-V material regions in the channel region are beneath the spacers.

9. The semiconductor device of claim 1, wherein the buffer layer has a thickness in a range from about 30 to about 150 nm.

10. The semiconductor device of claim 1, wherein the doped III-V material regions and the buffer layer are lattice matched to the discrete undoped III-V material region.

11. The semiconductor device of claim 1, wherein the buffer layer has a thickness in a range from about 100 to 150 nm.

12. The semiconductor device of claim 1, wherein the epitaxial contacts are formed over recesses within the substrate.

13. The semiconductor device of claim 1, wherein the doped III-V material regions comprise GaAs, InGaAS, AlGaInP, or any combination thereof.

14. The semiconductor device of claim 1, wherein the III-V material of the epitaxial contacts comprises a dopant in an amount that is the same as in the doped III-V material regions of the channel region.

15. The semiconductor device of claim 1, wherein the III-V material of the epitaxial contacts comprises a dopant in an amount that is different than a dopant in the doped III V material regions of the channel region.

16. The semiconductor device of claim 1, wherein a thickness of the discrete updoped III-V material region of the channel region is in a range from about 35 to about 45 nm.

17. A semiconductor device, comprising:

a gate arranged on a substrate;

a pair of epitaxial contacts comprising a III-V material arranged on opposing sides of the gate;

a channel region arranged underneath the gate and between the pair of epitaxial contacts, the channel region comprising a discrete undoped III-V material region between doped III-V material regions; and

a buffer layer between the channel region and the substrate, the buffer layer comprising carbon doped silicon.