Linear masking circuits for side-channel immunization of advanced encryption standard hardware

• US 10,256,973 B2
• Filed: 09/30/2016
• Issued: 04/09/2019
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kumar, Raghavan, Mathew, Sanu K., Varna, Avinash L., Suresh, Vikram B., Satpathy, Sudhir K.
• Primary Examiner(s): Hirl, Joseph P
• Assistant Examiner(s): Murphy, J. Brant
• Application Number:
  US15/283,000
• Publication Number:
  US 20180097618A1
• Time in Patent Office: 921 Days
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H04L 2209/046 of operations, operands or results of the operations
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0662 with particular pseudorandom sequence generator

Abstract

Described is an apparatus comprising an S-box circuitry operable to convert a value on an input into a value on an output in accordance with an Advanced Encryption Standard (AES) Rijndael S-box matrix. The apparatus also comprises a pseudo-random number generation (PRG) circuitry operable to provide a sequence of pseudo-random numbers on a first output and a registered copy of the sequence on a second output. The apparatus further comprises a mask circuitry operable to provide an XOR of a value on the output of the S box circuitry and a value on the first output of the PRG circuitry. The apparatus additionally comprises a mask removal circuitry operable to provide an XOR of a value on an output of the data register circuitry, a value coupled to an output of a key register circuitry, and a value on the second output of the PRG circuitry.

Claims

1. An apparatus comprising:

a first circuitry operable to convert a value on an input of the first circuitry into a value on an output of the first circuitry in accordance with an encryption matrix;

a second circuitry operable to provide a sequence of pseudo-random numbers on a first output of the second circuitry and a registered copy of the sequence on a second output of the second circuitry; and

a third circuitry operable to provide an XOR of a value on the output of the first circuitry and a value on the first output of the second circuitry onto an output of the third circuitry coupled to an input of a fourth circuitry.

2. The apparatus of claim 1, comprising:

a fifth circuitry operable to provide an XOR of a value on an output of the fourth circuitry, a value coupled to an output of a sixth circuitry, and a value on the second output of the second circuitry onto an output of the fifth circuitry coupled to the input of the first circuitry.

3. The apparatus of claim 2,

wherein a width of at least one of the following is an integer number of bytes:

the input of the first circuitry, the output of the first circuitry, the first output of the second circuitry, the second output of the second circuitry, the output of the third circuitry, the input of the fourth circuitry, the output of the fourth circuitry, the output of the sixth circuitry, and the output of the fifth circuitry.

4. The apparatus of claim 2,

wherein a width of at least one of the following is two bytes:

the input of the first circuitry, the output of the first circuitry, the first output of the second circuitry, the second output of the second circuitry, the output of the third circuitry, the input of the fourth circuitry, the output of the fourth circuitry, the output of the sixth circuitry, and the output of the fifth circuitry.

5. The apparatus of claim 2, comprising:

a seventh circuitry operable to convert a value on an input of the seventh circuitry into a value on an output of the seventh circuitry in accordance with a transformation process.

6. The apparatus of claim 5, comprising:

an eighth circuitry having at least a first input coupled to the output of the fourth circuitry, a second input coupled to the output of the seventh circuitry, a selection input, and an output coupled to the input of the fourth circuitry.

7. The apparatus of claim 5 comprising:

a ninth circuitry having at least a first input coupled to the output of the first circuitry, a second input coupled to the output of the third circuitry, a selection input, and an output coupled to the input of the seventh circuitry.

8. The apparatus of claim 2 comprising:

a tenth circuitry having at least a first input coupled to the output of the sixth circuitry, a second input coupled to an XOR of the output of the sixth circuitry and the output of the fourth circuitry, a selection input, and an output coupled to the input of the first circuitry.

9. The apparatus of claim 8, comprising:

an eleventh circuitry operable to provide an inversion of a value on an input of the eleventh circuitry to an output of the eleventh circuitry, the input of the eleventh circuitry being coupled to the output of the tenth circuitry;

a twelfth circuitry operable to provide an inversion of a value on an input of the twelfth circuitry to an output of the twelfth circuitry, the input of the twelfth circuitry being coupled to the output of the fourth circuitry; and

a thirteenth circuitry operable to perform an XOR of a value on the output of the twelfth circuitry and a value on the output of the twelfth circuitry.

10. The apparatus of claim 1,

wherein the second circuitry comprises a Linear-Feedback Shift Register (LFSR).

11. A system comprising a memory, a processor coupled to the memory, and a wireless interface for allowing the processor to communicate with another device, the system including the apparatus of claim 1.

12. A system comprising a memory, a processor coupled to the memory, and a wireless interface for allowing the processor to communicate with another device, the processor including:

a first circuitry operable to convert a value on an input of the first circuitry into a value on an output of the first circuitry in accordance with an encryption matrix;

a second circuitry operable to provide a sequence of pseudo-random numbers on a first output of the second circuitry and a registered copy of the sequence on a second output of the second circuitry; and

a third circuitry operable to provide an XOR of a value on the output of the first circuitry and a value on the first output of the second circuitry onto an output of the third circuitry coupled to an input of a fourth circuitry.

13. The system of claim 12, comprising:

a fifth circuitry operable to provide an XOR of a value on an output of the fourth circuitry, a value coupled to an output of a sixth circuitry, and a value on the second output of the second circuitry onto an output of the fifth circuitry coupled to the input of the first circuitry;

a seventh circuitry operable to convert a value on an input of the seventh circuitry into a value on an output of the seventh circuitry in accordance with a transformation process,

wherein the second circuitry comprises a Linear-Feedback Shift Register (LFSR).

14. The system of claim 13, comprising:

an eighth circuitry having at least a first input coupled to the output of the fourth circuitry, a second input coupled to the output of the seventh circuitry, a selection input, and an output coupled to the input of the fourth circuitry;

a ninth circuitry having at least a first input coupled to the output of the first circuitry, a second input coupled to the output of the third circuitry, a selection input, and an output coupled to the input of the seventh circuitry; and

a tenth circuitry having at least a first input coupled to the output of the sixth circuitry, a second input coupled to an XOR of the output of the sixth circuitry and the output of the fourth circuitry, a selection input, and an output coupled to the input of the first circuitry.

15. The system of claim 14, comprising:

an eleventh circuitry operable to provide an inversion of a value on an input of the eleventh circuitry to an output of the eleventh circuitry, the input of the eleventh circuitry being coupled to the output of the tenth circuitry;

a twelfth circuitry operable to provide an inversion of a value on an input of the twelfth circuitry to an output of the twelfth circuitry, the input of the twelfth circuitry being coupled to the output of the fourth circuitry; and

a thirteenth circuitry operable to perform an XOR of a value on the output of the twelfth circuitry and a value on the output of the twelfth circuitry.

16. An apparatus comprising:

a first circuitry operable to convert a value on an input of the first circuitry into a value on an output of the first circuitry in accordance with an encryption matrix;

a second circuitry operable to provide an inversion of a value on an input of the second circuitry to an output of the second circuitry;

a third circuitry operable to provide an inversion of a value on an input of the third circuitry to an output of the third circuitry; and

a fourth circuitry operable to perform an XOR of a value on the output of the second circuitry and a value on the output of the third circuitry,

wherein the input of the second circuitry is coupled to at least one of;

the input of the first circuitry and the output of the first circuitry; and

wherein the input of the second circuitry is coupled to an output of a key register circuitry.

17. The apparatus of claim 16,

wherein the input of the third circuitry is coupled to an output of a fifth circuitry.

18. The apparatus of claim 17, comprising:

a sixth circuitry having at least a first input coupled to an output of a seventh circuitry, a second input coupled to an XOR of the output of the seventh circuitry and the output of the fifth circuitry, a selection input, and an output coupled to the input of the first circuitry.