Systems and methods for tracing performance information from hardware realizations to models

• US 10,261,760 B1
• Filed: 12/05/2014
• Issued: 04/16/2019
• Est. Priority Date: 12/05/2013
• Status: Active Grant

• Current Assignee: The MathWorks, Inc.
• Original Assignee: The MathWorks, Inc.
• Inventors: Gu, Yongfeng
• Primary Examiner(s): Zhen, Li B.
• Assistant Examiner(s): Wheaton, Bradford F
• Application Number:
  US14/562,356
• Time in Patent Office: 1,593 Days
• Field of Search: 717105
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 8/35 model driven

Abstract

Systems and methods trace performance data generated by a hardware synthesis tool chain to model elements of a model. During code generation, an initial in-memory representation is generated for the model. The in-memory representation includes a plurality of nodes that correspond to the model elements. The in-memory representation is subjected to transformations and optimizations creating transitional in-memory representations and a final in-memory representation from which HDL code is generated. A graph builder constructs a genealogy graph that traces the transformations and optimizations. The genealogy graph includes graph objects corresponding to the nodes of the in-memory representations. The synthesis tool chain utilizes the HDL code to perform hardware synthesis. The synthesis tool chain also generates performance data. Utilizing the genealogy graph, the performance data is mapped to the nodes of the initial in-memory representation, and to the elements of the model.

Claims

1. A method comprising:

storing, in a memory, an executable model including a plurality of model elements;

generating an initial intermediate representation (IR) of the executable model, the initial IR including a plurality of initial IR nodes corresponding to the plurality of model elements of the executable model;

generating a plurality of transitional IRs and a final IR by applying a plurality of transforms to the initial IR and to selected ones of the plurality of transitional IRs, the plurality of transitional IRs including transitional IR nodes and the final IR including final IR nodes, the plurality of transforms including compiler operations;

automatically building, by a processor coupled to the memory, a genealogy graph for the initial IR, the plurality of transitional IRs, and the final IR, where

the genealogy graph includes a plurality of graph objects, the plurality of graph objects associated with respective ones of the initial IR nodes, the transitional IR nodes, and the final IR nodes,

the genealogy graph records changes to one or more of the initial IR nodes or to one or more of the transitional IR nodes occurring over time from one or more of the plurality of transforms, and

the plurality of graph objects are linked by edges that represent the plurality of transforms applied to the initial IR and to the selected ones of the plurality of transitional IRs, and tracing information associated with a first given IR node to a second given IR node utilizing the genealogy graph, wherein the first given IR node and the second given IR node are one of the plurality of initial IR nodes, the transitional IR nodes or the final IR nodes.

2. The method of claim 1 wherein a first transform of the plurality of transforms results in a deletion of a given transitional IR node, the method further comprising:

retaining the graph object of the genealogy graph that is associated with the given transitional IR node that is deleted.

3. The method of claim 1 wherein the plurality of graph objects include data that identifies the plurality of initial IR nodes, the transitional IR nodes, and the final IR nodes to which the plurality of graph object are associated.

4. The method of claim 1 further comprising:

annotating one or more of the edges of the genealogy graph with first information identifying respective ones of the plurality of transforms.

5. The method of claim 1 further comprising:

receiving data;

associating the data with the plurality of graph objects of the genealogy graph corresponding to the final IR nodes.

6. The method of claim 5 further comprising:

tracing the data associated with the final IR nodes to the initial IR nodes, utilizing one or more of the edges of the genealogy graph.

7. The method of claim 6 further comprising:

associating the data traced to the initial IR nodes with the plurality of model elements of the executable model.

8. The method of claim 7 wherein in the data associated with the final IR nodes is hardware performance data, the method further comprising:

generating hardware performance information for the executable model, the hardware performance information based on the hardware performance data associated with the plurality of model elements of the executable model.

9. The method of claim 1 further comprising:

generating a plurality of second transitional IRs and a second final IR by applying a plurality of second transforms to the initial IR and selected ones of the plurality of second transitional IRs, the plurality of second transitional IRs including second transitional IR nodes and the second final IR including second final IR nodes;

updating the genealogy graph to include a plurality of second graph objects, the plurality of second graph objects associated with respective ones of the second transitional IR nodes and the second final IR nodes;

associating data with the plurality of graph objects of the genealogy graph corresponding to the final IR nodes; and

tracing the data associated with the plurality of graph objects corresponding to the final IR nodes to one or more of the second final IR nodes.

10. The method of claim 9 wherein the final IR has a structure suitable for generating code conforming to a first programming language, and the second final IR has a structure suitable for generating code conforming to a second programming language.

21. The method of claim 1 where the compiler operations include at least one of:

procedure in-lining;

a loop transformation,

a global optimization;

a local optimization,

a register allocation;

or

a target-dependent optimization.

11. One or more non-transitory computer-readable media comprising programming instructions, the program instructions, when executed by a processor, instructing the processor to:

store, in a memory coupled to the processor, an executable model including a plurality of model elements;

generate a first intermediate representation (IR) of the executable model, the first IR including a plurality of first IR nodes associated with the plurality of model elements of the executable model;

apply one or more transforms to the first IR to produce a second IR, the second IR including a plurality of second IR nodes, the one or more transforms including compiler operations;

automatically build, by the processor, a genealogy graph for the executable model, where the genealogy graph includes

a plurality of graph objects, the plurality of graph objects associated with respective ones of the plurality of first IR nodes and the plurality of second IR nodes, and

pointers among the plurality of graph objects, the pointers linking the plurality of first IR nodes to the plurality of second IR nodes based on the one or more transforms applied to the first IR to produce the second IR, and the genealogy graph records changes to one or more of the plurality of first IR nodes or to one or more of the plurality of second IR nodes occurring over time from the one or more transforms;

associate information with a given second IR node of the plurality of second IR nodes; and

trace the information associated with the given second IR node to a given first IR node of the plurality of first IR nodes utilizing the genealogy graph.

12. The one or more computer-readable media of claim 11 wherein the program instructions further instruct the processor to:

annotate one or more of the pointers of the genealogy graph with first information identifying the one or more transforms.

13. The one or more computer-readable media of claim 11 wherein the pointers link the plurality of first IR nodes to the plurality of second IR nodes through a plurality of intermediate graph objects associated with IR nodes of transitional IRs.

14. The one or more computer-readable media of claim 13 wherein the first IR is an initial IR for the executable model, and the second IR is a final IR having a structure suitable for code generation.

15. The one or more computer-readable media of claim 11 wherein the program instructions further instruct the processor to:

trace the information from the given first IR node to one or more of the plurality of model elements of the executable model.

22. The one or more computer-readable media of claim 11 where the compiler operations include at least one of:

procedure in-lining;

a loop transformation,

a global optimization;

a local optimization,

a register allocation;

or

a target-dependent optimization.

16. An apparatus comprising:

a memory storing an executable model, the executable model including a plurality of model elements; and

a processor coupled to the memory, the processor configured to;

generate a first intermediate representation (IR) of the executable model, the first IR including a plurality of first IR nodes associated with the plurality of model elements of the executable model;

apply one or more transforms to the first IR to produce a second IR, the second IR including a plurality of second IR nodes, the one or more transforms including compiler operations;

automatically build a genealogy graph for the executable model, where the genealogy graph includes

a plurality of graph objects, the plurality of graph objects associated with respective ones of the plurality of first IR nodes and the plurality of second IR nodes, and

pointers among the plurality of graph objects, the pointers linking the plurality of first IR nodes to the plurality of second IR nodes based on the one or more transforms applied to the first IR to produce the second IR, and the genealogy graph records changes to one or more of the plurality of first IR nodes or to one or more of the plurality of second IR nodes occurring over time from the one or more transforms;

associate information with a particular first IR node of the plurality of first IR nodes; and

trace the information associated with the particular first IR node to a particular second IR node of the plurality of second IR nodes utilizing the genealogy graph.

17. The apparatus of claim 16 wherein the one or more transforms deletes a given first IR node, the processor further configured to:

retain the graph object of the genealogy graph that is associated with the given first IR node that is deleted.

18. The apparatus of claim 16 wherein the processor is further configured to:

annotate one or more of the pointers of the genealogy graph with first information identifying the one or more transforms.

19. The apparatus of claim 16 wherein the pointers link the plurality of first IR nodes to the plurality of second IR nodes through a plurality of intermediate graph objects associated with IR nodes of transitional IRs.

20. The apparatus of claim 19 wherein the first IR is an initial IR for the executable model, and the second IR is a final IR having a structure suitable for code generation.

23. The apparatus of claim 16 where the compiler operations include at least one of:

procedure in-lining;

a loop transformation,

a global optimization;

a local optimization,

a register allocation;

or

a target-dependent optimization.