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Communication system for transmitting and receiving control frames

  • US 10,261,924 B2
  • Filed: 08/03/2016
  • Issued: 04/16/2019
  • Est. Priority Date: 08/03/2016
  • Status: Active Grant
First Claim
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1. A communication system connected between a baseband processor and a Joint Electron Devices Engineering Council (JEDEC) Standards Document (JESD) 204B compliant serial interface for transmitting and receiving first and second JESD control frames corresponding to first and second data, respectively, the communication system comprising:

  • a set of configuration registers that receives and stores at least one of first and second control data from the baseband processor, and outputs at least one of first and second control-configuration data based on the first and second control data, respectively;

    a packet processor that (i) receives at least one receive-configuration packet, (ii) receives the first control-configuration data from the set of configuration registers, and generates at least one transmit-configuration packet and at least one receive-configuration data based on the first control-configuration data and the at least one receive-configuration packet, respectively;

    a configuration sampler that (i) receives at least one of first and second frame-configuration data, (ii) identifies first and second frame-structure data based on the first and second frame-configuration data, respectively, and (iii) outputs at least one of the first and second frame-structure data;

    a timing monitor circuit that receives at least one of first and second frame-timing data and outputs at least one of first and second timing signals, respectively;

    a control-frame processor that (i) receives the second JESD control frame, (ii) is connected to the packet processor, the configuration sampler, and the timing monitor circuit, (iii) receives the at least one transmit-configuration packet, the at least one of the first and second frame-structure data, and the at least one of the first and second timing signals, respectively, and (iv) generates the first JESD control frame and the at least one receive-configuration packet, wherein the first JESD control frame is generated based on the at least one transmit-configuration packet, the first timing signal, and the first frame-structure data, and wherein the at least one receive-configuration packet is generated based on the second JESD control frame, the second timing signal, and the second frame-structure data; and

    a transceiver connected to the serial interface, the baseband processor, and the control frame processor, wherein the transceiver (i) receives the first JESD control frame including first configuration data, the second JESD control frame including second configuration data, and the first data, respectively, (ii) identifies the first and second frame-configuration data based on the first and second configuration data, respectively, and the first and second frame-timing data based on the first and second configuration data, respectively, and (iii) outputs the at least one of the first and second frame-configuration data, the at least one of the first and second frame-timing data, the first JESD control frame, and the first data, wherein the first JESD control frame includes the first configuration data and the first control data, and wherein the serial interface receives the first JESD control frame and the first data, thereby transmitting and receiving the first and second JESD control frames corresponding to the first and second data, respectively.

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