Component placement with repacking for programmable logic devices

• US 10,262,096 B2
• Filed: 02/28/2014
• Issued: 04/16/2019
• Est. Priority Date: 02/28/2014
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Shen, Yinan, Zhao, Jun
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): Bowers, Brandon
• Application Number:
  US14/194,484
• Publication Number:
  US 20150248512A1
• Time in Patent Office: 1,873 Days
• Field of Search: 716106
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Systems and methods are disclosed herein to provide improved placement of components in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes determining a layout comprising positions of components of the PLD configured to perform the operations. The method also includes performing a timing analysis on the layout. The method also includes selectively adjusting the positions of the components using the timing analysis. Related systems and non-transitory machine-readable mediums are also provided.

Claims

1. A method comprising:

receiving in a processor, a design identifying operations to be performed by a programmable logic device (PLD), with logic blocks in pre-determined physical locations of the PLD;

packing, in the processor, each of a plurality of components of the PLD into a respective one of a plurality of logic groups;

determining, in the processor, a layout comprising assigned positions of the plurality of logic groups of the PLD configured to perform the operations;

routing connections between the plurality of components;

performing, in the processor, a timing analysis on the layout comprising both the assigned positions of the plurality of logic groups and the routed connections;

selectively adjusting, in the processor, assigned positions of the plurality of components in the determined layout by repacking at least one of the plurality of components into another logic group of the plurality of logic groups using the timing analysis;

generating an adjusted layout comprising the adjusted assigned positions of the plurality of components of the PLD, for configuring the PLD to perform the operations;

storing the adjusted layout for configuring the PLD to perform the operations; and

providing the PLD programmed based on the adjusted layout.

2. The method of claim 1, wherein the adjusting comprises:

identifying a signal path between at least a subset of the plurality of components that does not satisfy a timing requirement of the design based on the timing analysis;

identifying a target location in the PLD for at least one of the plurality of components in the signal path that satisfies the timing requirement; and

adjusting the position of the component to the target location.

3. The method of claim 2, wherein the target location corresponds to a particular component position within a particular logic block of the PLD.

4. The method of claim 1, wherein the determining comprises assigning the plurality of logic groups to selected logic blocks of the PLD.

5. The method of claim 4, wherein the adjusting comprises moving each adjusted component from its first assigned logic block to a second different logic block.

6. The method of claim 4, wherein the plurality of components comprises lookup tables implemented in the logic blocks.

7. The method of claim 1, wherein the determining comprises performing a simulated annealing placement process to determine the positions of the plurality of components.

8. The method of claim 7, wherein the timing analysis and the adjusting are performed during and/or after the simulated annealing placement process, the method further comprising providing a configuration file containing the adjusted layout for configuring the PLD to perform the operations.

9. The method of claim 7, further comprising routing connections between the plurality of components after the simulated annealing placement process.

10. A system comprising:

a processor; and

a memory adapted to store a plurality of computer readable instructions which when executed by the processor are adapted to cause the system to perform a computer-implemented method comprising;

receiving a design identifying operations to be performed by a programmable logic device (PLD), with logic blocks in pre-determined physical locations of the PLD,

packing each of a plurality of components of the PLD into a respective one of a plurality of logic groups,

determining a layout comprising assigned positions of the plurality of logic groups of the PLD configured to perform the operations,

routing connections between the plurality of components,

performing a timing analysis on the layout comprising both the assigned positions of the plurality of logic groups and the routed connections,

selectively adjusting assigned positions of the plurality of components in the determined layout by repacking at least one of the plurality of components into another logic group of the plurality of logic groups based on the timing analysis,

generating an adjusted layout comprising the adjusted assigned positions of the plurality of components of the PLD, for configuring the PLD to perform the operations,

storing the adjusted layout for configuring the PLD to perform the operations, and

programming the PLD with the adjusted layout.

11. The system of claim 10, wherein the adjusting comprises:

identifying a signal path between at least a subset of the plurality of components that does not satisfy a timing requirement of the design based on the timing analysis;

identifying a target location in the PLD for at least one of the plurality of components in the signal path that satisfies the timing requirement; and

adjusting the position of the component to the target location.

12. The system of claim 11, wherein the target location corresponds to a particular component position within a particular logic block of the PLD.

13. The system of claim 10, wherein the determining comprises assigning the plurality of logic groups to logic blocks of the PLD, and wherein the adjusting comprises moving each adjusted component from its first assigned logic block to a second different logic block.

14. The system of claim 10, wherein the determining comprises performing a simulated annealing placement process to determine the positions of the plurality of components.

15. The system of claim 14, wherein the timing analysis and the adjusting are performed during and/or after the simulated annealing placement process.

16. The system of claim 14, wherein the method further comprises routing connections between the plurality of components after the simulated annealing placement process.

17. A method comprising:

receiving in a processor, a design identifying operations to be performed by a programmable logic device (PLD), with logic blocks in pre-determined physical locations of the PLD;

packing, in the processor, each of a plurality of components of the PLD into a respective one of a plurality of logic groups;

determining, in the processor, a layout comprising assigned positions of the plurality of logic groups of the PLD configured to perform the operations;

routing connections between the plurality of components;

performing, in the processor, a timing analysis on the layout comprising both the assigned positions of the plurality of logic groups and the routed connections;

selectively adjusting, in the processor, assigned positions of the plurality of components in the determined layout by repacking at least one of the plurality of components into another logic group of the plurality of logic groups using the timing analysis;

generating an adjusted layout comprising the adjusted assigned positions of the plurality of components of the PLD, for configuring the PLD to perform the operations;

storing the adjusted layout for configuring the PLD to perform the operations; and

programming the PLD with the adjusted layout.

18. A non-transitory machine-readable medium storing a plurality of machine-readable instructions which when executed by one or more processors of a computer system are adapted to cause the computer system to perform the method of claim 17.

19. The method of claim 18, wherein:

the adjusting comprises;

identifying a signal path between at least a subset of the plurality of components that does not satisfy a timing requirement of the design based on the timing analysis;

identifying a target location in the PLD for at least one of the plurality of components in the signal path that satisfies the timing requirement; and

adjusting the position of the component to the target location; and

the determining comprises performing a simulated annealing placement process to determine the positions of the plurality of components.

20. The method of claim 18, further comprising providing the PLD programmed with the adjusted layout.