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Secure processor with resistance to external monitoring attacks

  • US 10,262,141 B2
  • Filed: 12/30/2016
  • Issued: 04/16/2019
  • Est. Priority Date: 12/04/2009
  • Status: Active Grant
First Claim
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1. A secure processor comprising:

  • a secure non-volatile storage to store a secret value;

    a cache; and

    a cryptographic hardware component operatively coupled to the secure non-volatile storage and the cache, wherein the cryptographic hardware component protects against leakage of sensitive data and against differential power analysis by performing the following for the sensitive data received from an unsecure memory, wherein the sensitive data comprises an encrypted data segment and a validator;

    derives an initial key based at least in part on an identifier associated with the encrypted data segment and the secret value, wherein the initial key is derived using a path through a key tree that is based at least in part on the identifier and on the secret value;

    verifies, using the validator, whether the encrypted data segment has been modified without re-using the secret value;

    derives a first decryption key from the initial key;

    responsive to verifying that the encrypted data segment has not been modified, decrypts the encrypted data segment using the first decryption key to produce a decrypted data segment;

    applies an entropy distribution operation to the first decryption key to derive a second decryption key; and

    decrypts an additional encrypted data segment of the sensitive data with the second decryption key.

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