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DRAM adjacent row disturb mitigation

  • US 10,262,717 B2
  • Filed: 11/03/2017
  • Issued: 04/16/2019
  • Est. Priority Date: 10/21/2015
  • Status: Active Grant
First Claim
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1. A semiconductor memory integrated circuit comprising an array of memory cells with addressable rows, (i) wherein each memory cell requires regular refresh operations, and (ii) wherein each addressable row is physically adjacent to at least one other addressable row, the semiconductor memory integrated circuit comprising:

  • (A) a command path circuit, comprising;

    (i) a plurality of command inputs,(ii) a command decoder circuit coupled to the command inputs,(iii) a refresh control logic circuit coupled to the command decoder circuit, and(iv) a refresh counter circuit coupled to the refresh control logic circuit;

    (B) an address path circuit, comprising;

    (i) a plurality of address inputs,(ii) an address logic circuit coupled to the address inputs;

    (C) a target row refresh (TRR) circuit, comprising;

    (i) a first in first out content addressable memory (FIFO CAM) circuit coupled to the address inputs and the command decoder,(ii) a bank/block/row content addressable memory (BBR CAM) circuit coupled to the FIFO CAM circuit and the refresh counter,(iii) a plurality of watch list counter circuits coupled to the BRR CAM circuit,(iv) a plurality of tenure counter circuits coupled to the BRR CAM circuit,(v) a TRR queue circuit coupled to the BRR CAM circuit, and(vi) a TRR logic circuit coupled to the FIFO CAM circuit, the BBR CAM circuit, the TRR queue circuit, the watch list counter circuits, the tenure counter circuits, and the refresh control logic circuit; and

    (D) a plurality of memory banks, wherein;

    (i) each memory bank comprises a portion of the array of memory cells, and(ii) each memory bank is coupled to the refresh counter circuit, the address logic circuit, and the TRR queue circuit.

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