DRAM adjacent row disturb mitigation
First Claim
1. A semiconductor memory integrated circuit comprising an array of memory cells with addressable rows, (i) wherein each memory cell requires regular refresh operations, and (ii) wherein each addressable row is physically adjacent to at least one other addressable row, the semiconductor memory integrated circuit comprising:
- (A) a command path circuit, comprising;
(i) a plurality of command inputs,(ii) a command decoder circuit coupled to the command inputs,(iii) a refresh control logic circuit coupled to the command decoder circuit, and(iv) a refresh counter circuit coupled to the refresh control logic circuit;
(B) an address path circuit, comprising;
(i) a plurality of address inputs,(ii) an address logic circuit coupled to the address inputs;
(C) a target row refresh (TRR) circuit, comprising;
(i) a first in first out content addressable memory (FIFO CAM) circuit coupled to the address inputs and the command decoder,(ii) a bank/block/row content addressable memory (BBR CAM) circuit coupled to the FIFO CAM circuit and the refresh counter,(iii) a plurality of watch list counter circuits coupled to the BRR CAM circuit,(iv) a plurality of tenure counter circuits coupled to the BRR CAM circuit,(v) a TRR queue circuit coupled to the BRR CAM circuit, and(vi) a TRR logic circuit coupled to the FIFO CAM circuit, the BBR CAM circuit, the TRR queue circuit, the watch list counter circuits, the tenure counter circuits, and the refresh control logic circuit; and
(D) a plurality of memory banks, wherein;
(i) each memory bank comprises a portion of the array of memory cells, and(ii) each memory bank is coupled to the refresh counter circuit, the address logic circuit, and the TRR queue circuit.
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Accused Products
Abstract
The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate.
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Citations
8 Claims
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1. A semiconductor memory integrated circuit comprising an array of memory cells with addressable rows, (i) wherein each memory cell requires regular refresh operations, and (ii) wherein each addressable row is physically adjacent to at least one other addressable row, the semiconductor memory integrated circuit comprising:
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(A) a command path circuit, comprising; (i) a plurality of command inputs, (ii) a command decoder circuit coupled to the command inputs, (iii) a refresh control logic circuit coupled to the command decoder circuit, and (iv) a refresh counter circuit coupled to the refresh control logic circuit; (B) an address path circuit, comprising; (i) a plurality of address inputs, (ii) an address logic circuit coupled to the address inputs; (C) a target row refresh (TRR) circuit, comprising; (i) a first in first out content addressable memory (FIFO CAM) circuit coupled to the address inputs and the command decoder, (ii) a bank/block/row content addressable memory (BBR CAM) circuit coupled to the FIFO CAM circuit and the refresh counter, (iii) a plurality of watch list counter circuits coupled to the BRR CAM circuit, (iv) a plurality of tenure counter circuits coupled to the BRR CAM circuit, (v) a TRR queue circuit coupled to the BRR CAM circuit, and (vi) a TRR logic circuit coupled to the FIFO CAM circuit, the BBR CAM circuit, the TRR queue circuit, the watch list counter circuits, the tenure counter circuits, and the refresh control logic circuit; and (D) a plurality of memory banks, wherein; (i) each memory bank comprises a portion of the array of memory cells, and (ii) each memory bank is coupled to the refresh counter circuit, the address logic circuit, and the TRR queue circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification