DRAM adjacent row disturb mitigation

• US 10,262,717 B2
• Filed: 11/03/2017
• Issued: 04/16/2019
• Est. Priority Date: 10/21/2015
• Status: Active Grant

• Current Assignee: Invensas LLC (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Fisch, David Edward, Plants, William C.
• Primary Examiner(s): Cho, Sung
• Application Number:
  US15/803,710
• Publication Number:
  US 20180114561A1
• Time in Patent Office: 529 Days
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 11/4078 Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells protection of memory contents during checking or testing G11C29/52
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/06 Acceleration testing
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches

Abstract

The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate.

Claims

1. A semiconductor memory integrated circuit comprising an array of memory cells with addressable rows, (i) wherein each memory cell requires regular refresh operations, and (ii) wherein each addressable row is physically adjacent to at least one other addressable row, the semiconductor memory integrated circuit comprising:

(A) a command path circuit, comprising;

(i) a plurality of command inputs,

(ii) a command decoder circuit coupled to the command inputs,

(iii) a refresh control logic circuit coupled to the command decoder circuit, and

(iv) a refresh counter circuit coupled to the refresh control logic circuit;

(B) an address path circuit, comprising;

(i) a plurality of address inputs,

(ii) an address logic circuit coupled to the address inputs;

(C) a target row refresh (TRR) circuit, comprising;

(i) a first in first out content addressable memory (FIFO CAM) circuit coupled to the address inputs and the command decoder,

(ii) a bank/block/row content addressable memory (BBR CAM) circuit coupled to the FIFO CAM circuit and the refresh counter,

(iii) a plurality of watch list counter circuits coupled to the BRR CAM circuit,

(iv) a plurality of tenure counter circuits coupled to the BRR CAM circuit,

(v) a TRR queue circuit coupled to the BRR CAM circuit, and

(vi) a TRR logic circuit coupled to the FIFO CAM circuit, the BBR CAM circuit, the TRR queue circuit, the watch list counter circuits, the tenure counter circuits, and the refresh control logic circuit; and

(D) a plurality of memory banks, wherein;

(i) each memory bank comprises a portion of the array of memory cells, and

(ii) each memory bank is coupled to the refresh counter circuit, the address logic circuit, and the TRR queue circuit.

2. The semiconductor memory integrated circuit of claim 1, further comprising a mode register circuit coupled to the address logic circuit and the TRR logic circuit.

3. The semiconductor memory integrated circuit of claim 1, further comprising a non-volatile memory circuit coupled to the TRR logic circuit.

4. The semiconductor memory integrated circuit of claim 1, wherein the FIFO CAM circuit further comprises:

(i) a first in first out (FIFO) logic circuit;

(ii) a content addressable memory (CAM) logic circuit;

(iii) a plurality of address entry memory locations each coupled to the FIFO logic and the CAM logic, and configured to receive addresses from the plurality of address inputs; and

(iv) a plurality of match flag circuits each associated with and coupled to one of the address entry memory locations.

5. The semiconductor memory integrated circuit of claim 1, wherein the BBR CAM circuit further comprises:

(i) a random access memory (RAM) logic circuit;

(ii) a content addressable memory (CAM) logic circuit; and

(iii) a plurality of tracked address memory locations each coupled to the RAM logic and the CAM logic, and configured to receive addresses from the FIFO CAM circuit.

6. The semiconductor memory integrated circuit of claim 5, wherein:

(i) each watch list counter circuit is associated with and coupled to one of the tracked address memory locations; and

(ii) each tenure counter circuit is associated with and coupled to one of the tracked address memory locations.

7. The semiconductor memory integrated circuit of claim 1, wherein the TRR queue circuit further comprises:

(i) a queue control logic circuit; and

(ii) a plurality of queued address memory locations each coupled to the queue control logic circuit, and configured to receive addresses from the BBR CAM circuit.

8. The semiconductor memory integrated circuit of claim 7, wherein each memory bank further comprises:

(i) a multiplexer circuit coupled to the refresh counter, the TTR queue circuit, and the address logic circuit;

(ii) a bank row decoder circuit coupled to the multiplexer circuit and to the portion of the array of memory cells; and

(iii) a plurality of bit line sense amplifier (BLSA) circuits coupled to the memory cells.