Nonvolatile memory structure

• US 10,262,746 B2
• Filed: 08/31/2016
• Issued: 04/16/2019
• Est. Priority Date: 01/19/2016
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Chen, Ying-Je, Chen, Wei-Ren, Sun, Wein-Town
• Primary Examiner(s): Kalam, Abul
• Application Number:
  US15/252,244
• Publication Number:
  US 20170207228A1
• Time in Patent Office: 958 Days
• Field of Search: None
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 : characterised by the top-view layout
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell

Abstract

A nonvolatile memory structure includes a first PMOS transistor and a first floating-gate transistor on a first active region in a substrate, a second PMOS transistor and a second floating-gate transistor on a second active region in the substrate, and an n-type erase region in the substrate. A source line connects with sources of the first and the second PMOS transistors. A bit line connects with drains of the first and the second floating-gate transistors. A word line connects with first and the second select gates in the first and the second PMOS transistors respectively. An erase line connects with the n-type erase region. The first floating-gate transistor includes a first floating gate with an extended portion extending on a first portion of the n-type erase region. The second floating-gate transistor includes a second floating gate with an extended portion extending on a second portion of the n-type erase region.

Claims

1. A 2-cells-per-bit nonvolatile memory structure, comprising:

a substrate comprising a first active region, a second active region, and an n-type erase region, wherein the n-type erase region is insulated from the first active region and the second active region;

a first PMOS transistor and a first floating-gate transistor on the first active region respectively, wherein the first PMOS transistor includes a first select gate and a first source, the first floating-gate transistor includes a first drain and a first floating gate between the first select gate and the n-type erase region, the first floating gate comprises an extended portion extending on a first portion of the n-type erase region, and the extended portion of the first floating gate has an extending direction parallel to an extending direction of the first active region;

a second PMOS transistor and a second floating-gate transistor on the second active region respectively, wherein the second PMOS transistor includes a second select gate and a second source, the second floating-gate transistor includes a second drain and a second floating gate between the second select gate and the n-type erase region, the second floating gate comprises an extended portion extending on a second portion of the n-type erase region, and the extended portion of the second floating gate has an extending direction parallel to an extending direction of the second active region;

a source line connecting with the first source of the first PMOS transistor and the second source of the second PMOS transistor;

a bit line connecting with the first drain of the first floating-gate transistor and the second drain of the second floating-gate transistor;

a word line connecting with the first select gate and the second select gate; and

an erase line connecting with the n-type erase region.

2. The nonvolatile memory structure according to claim 1, wherein the first floating gate and the second floating gate are erased by Fowler-Nordheim (FN) tunnelling.

3. The nonvolatile memory structure according to claim 1, wherein the first floating gate and the second floating gate are programmed by channel hot electron (CHE) program.

4. The nonvolatile memory structure according to claim 1, further comprising a p-type well surrounding the n-type erase region.

5. The nonvolatile memory structure according to claim 1, further comprising a p-type well under and surrounding the n-type erase region.

6. The nonvolatile memory structure according to claim 1, further comprising a salicide blocking (SAB) layer on each of the first floating gate and the second floating gate.

7. The nonvolatile memory structure according to claim 1, wherein an overlap area between the first floating gate and the first active region is A1, an overlap area between the first floating gate and the n-type erase region is A2, and a ratio of A1 to a sum of A1 and A2 is more than 75%.

8. The nonvolatile memory structure according to claim 1, wherein an overlap area between the second floating gate and the second active region is A3, an overlap area between the second floating gate and the n-type erase region is A4, and a ratio of A3 to a sum of A3 and A4 is more than 75%.

9. The nonvolatile memory structure according to claim 1, further comprising an additional portion in the extended portion of the first floating gate on the first portion of the n-type erase region.

10. The nonvolatile memory structure according to claim 1, further comprising an additional portion in the extended portion of the second floating gate on the second portion of the n-type erase region.

11. The nonvolatile memory structure according to claim 1, wherein the extended portions of the first floating gate and the second floating gate are each independently across the n-type erase region.

12. The nonvolatile memory structure according to claim 1, wherein the first active region and the second active region under the word line are in contact with each other.

13. The nonvolatile memory structure according to claim 1, wherein the first active region and the second active region under the bit line are in contact with each other.

14. The nonvolatile memory structure according to claim 1, wherein the first active region and the second active region are spaced apart from each other.

15. The nonvolatile memory structure according to claim 1, wherein the extended portion of the first floating gate overlaps a portion of the first active region.

16. The nonvolatile memory structure according to claim 1, wherein the extended portion of the second floating gate overlaps a portion of the second active region.

17. The nonvolatile memory structure according to claim 1, wherein the extended portions of the first floating gate and the second floating gate are disposed between the first active region and the second active region.

18. The nonvolatile memory structure according to claim 1, wherein the extended portions of the first floating gate and the second floating gate are disposed outside the first active region and the second active region.

19. The nonvolatile memory structure according to claim 1, wherein the n-type erase region comprises two isolated regions, the extended portion of the first floating gate extends on one of the isolated regions, and the extended portion of the second floating gate extends on another of the isolated regions.

20. The nonvolatile memory structure according to claim 1, wherein the extended portion of the first floating gate has an extending direction parallel to an extending direction of the first active region.

21. The nonvolatile memory structure according to claim 1, wherein the extended portion of the first floating gate has an extending direction perpendicular to an extending direction of the first active region.

22. The nonvolatile memory structure according to claim 1, wherein the extended portion of the second floating gate has an extending direction parallel to an extending direction of the second active region.

23. The nonvolatile memory structure according to claim 1, wherein the extended portion of the second floating gate has an extending direction perpendicular to an extending direction of the second active region.

24. An array comprising a plurality of nonvolatile memory structures according to claim 1, in which two of the nonvolatile memory structures share one of the n-type erase regions.