Visible alignment markers/landmarks for CAD-to-silicon backside image alignment

• US 10,262,950 B1
• Filed: 03/06/2018
• Issued: 04/16/2019
• Est. Priority Date: 10/17/2017
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Alston, Michael Duane, Bunnalim, Hadi, Endrinal, Lesly Zaren Venturina, Malabry, Mickael Sebastien Alain, Ranganathan, Lavakumar, Salem, Rami Fathy Amin Gomaa
• Primary Examiner(s): Ahmed, Selim U
• Assistant Examiner(s): Stevenson, Andre C
• Application Number:
  US15/913,784
• Publication Number:
  US 20190115301A1
• Time in Patent Office: 406 Days
• CPC Class Codes: H01L 2027/11874 Layout specification, i.e. inner core region
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/30 Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7834 : with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A metal oxide semiconductor (MOS) integrated circuit (IC) has a plurality of fiducial standard cells of different cell sizes. The different cell sizes are non-equally utilized. The plurality of fiducial standard cells are placed to have a random offset from a uniform global placement pattern. Each of the fiducial standard cells has at least four power rails and various sets of active regions. The power rails extend in a first direction. The active regions are provided adjacent to the power rails but are disconnected from contacts and interconnects and thus do not draw power from the power rails. Instead, the active regions are disjoint and collinear thereby creating islands of active regions among spacings of inactive regions. These inactive regions more easily allow electromagnetic radiation to pass through thereby allowing the MOS fiducial standard cell to be visible for a CAD-to-silicon backside image alignment even with 7 nm feature sizes.

Claims

1. A metal oxide semiconductor (MOS) integrated circuit (IC), comprising:

a plurality of fiducial standard cells, wherein the plurality of fiducial standard cells include a plurality of cell sizes, the plurality of cell sizes are non-equally utilized among the plurality of fiducial standard cells, and the plurality of fiducial standard cells are placed to have a random offset from a uniform global placement pattern, wherein each cell size of the plurality of cell sizes of the plurality of fiducial standard cells has one or more openings in a diffusion layer of an active region to allow for reflections of a laser beam from a metal layer.

2. The MOS IC of claim 1, wherein each cell size of the plurality of cell sizes of the plurality of fiducial standard cells differ in at least one of an x-direction and a y-direction.

3. The MOS IC of claim 1, wherein the metal layer is not connected to the active region for each cell size of the plurality of cell sizes of the plurality of fiducial standard cells.

4. The MOS IC of claim 1, wherein each cell size the plurality of cell sizes differs in the openings in the diffusion layer of the active region.

5. The MOS IC of claim 1, wherein the plurality of fiducial standard cells are further placed to allow a reduced number of fiducial standard cells to be viewable within a viewing window aperture positioned at a plurality of positions on the MOS IC.

6. The MOS IC of claim 1, wherein each cell size of the plurality of cell sizes is non-equally utilized among the plurality of fiducial standard cells so that the fiducial standard cell having a largest cell size has a highest utilization.

7. The MOS IC of claim 1, wherein the plurality of fiducial standard cells are placed to have a random offset from a uniform global placement pattern by a placement of each of the plurality of fiducial standard cells to have a random dithering in distance from the uniform global placement pattern along at least one of an x-direction and a y-direction.

8. The MOS IC of claim 1, wherein the uniform global placement pattern comprises one of a non-rotated square pattern, a rotated square pattern, a non-rotated hexagonal pattern, and a rotated hexagonal pattern.

9. The MOS IC of claim 1, wherein the uniform global placement pattern is scaled to allow a reduced number of fiducial standard cells to be viewable within a viewing window aperture.

10. The MOS IC of claim 1, wherein the plurality of cell sizes of the plurality of fiducial standard cells comprises:

at least four power rails extending in a first direction across the fiducial standard cells, wherein each of the at least four power rails is coupled to a first voltage source or a second voltage source different than the first voltage source;

and wherein the active region includes one or more sets of active regions adjacent each of the at least four power rails, wherein each set of the one or more sets of active regions is collinear in the first direction, wherein at least one set of active regions includes at least two disjoint active regions, and wherein each set of the one or more sets of the active regions is disconnected from contacts and interconnects to the metal layer.

11. The MOS IC of claim 10, wherein the at least two disjoint active regions of the at least one set of the active regions are separated by less than 300 nm.

12. The MOS IC of claim 10, wherein each set of the one or more sets of active regions are aligned in a second direction orthogonal to the first direction.

13. The MOS IC of claim 10, wherein the at least two disjoint active regions of the at least one of the active regions comprises an active region on a first side of the fiducial standard cells and an active region on a second side of the fiducial standard cells.

14. The MOS IC of claim 10, wherein at least one of the active regions comprises one active region extending in the first direction across the fiducial standard cells.

15. The MOS IC of claim 10, wherein each cell size of the plurality of cell sizes of the plurality of fiducial standard cells further comprises a plurality of floating gate interconnects extending in a second direction across the fiducial standard cells, the second direction being orthogonal to the first direction.

16. The MOS IC of claim 10, wherein at least one of the active regions include at least three disjoint active regions.

17. The MOS IC of claim 16, wherein adjacent pairs of active regions of the at least three disjoint active regions are separated by less than 300 nm.

18. The MOS IC of claim 16, wherein the at least three disjoint active regions of the at least one of the active regions comprise an active region on a first side of the fiducial standard cells, an active region in a central portion of the fiducial standard cells, and an active region on a second side of the fiducial standard cells.

20. The MOS IC of claim 1, wherein a total area of the plurality of fiducial standard cells is less than 0.1% of an area of the MOS IC.

19. A method of placing a plurality of fiducial standard cells in a metal oxide semiconductor (MOS) integrated circuit (IC), comprising:

determining a region of the MOS IC for placing the plurality of fiducial standard cells, wherein the region has an x-direction and a y-direction;

subtracting a dither range in the x-direction from one half of a maximum distance in the x-direction between a non-fiducial standard cell and one of the plurality of fiducial standard cells to generate an x-direction half-stepping distance;

subtracting a dither range in the y-direction from one half of a maximum distance in the y-direction between a non-fiducial standard cell and one of the plurality of fiducial standard cells to generate a y-direction half-stepping distance;

determining a random dither in the x-direction, wherein the random dither in the x-direction ranges from a minus half to a positive half times the dither range in the x-direction;

determining a random dither in the y-direction, wherein the random dither in the y-direction ranges from a minus half to a positive half times the dither range in the y-direction;

stepping through the x-direction of the region by successively adding twice the x-direction half-stepping distance by the random dither in the x-direction to determine a plurality of placement positions in the x-direction;

stepping through the y-direction of the region by successively adding twice the y-direction half-stepping distance by the random dither in the y-direction to determine a plurality of placement positions in the y-direction; and

placing the plurality of fiducial standard cells at locations based on the plurality of placement positions in the x-direction and the plurality of placement positions in the y-direction.