Photodiode with different electric potential regions for image sensors

• US 10,263,032 B2
• Filed: 02/29/2016
• Issued: 04/16/2019
• Est. Priority Date: 03/04/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Wan, Chung Chun
• Primary Examiner(s): Pyo, Kevin K
• Application Number:
  US15/056,752
• Publication Number:
  US 20160365380A1
• Time in Patent Office: 1,142 Days
• Field of Search: 2502141, 2502081, 257292, 257294, 257463, 257464, 348294, 348296, 348308
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 23/54 Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

An image sensor pixel is disclosed. The pixel may include a photodiode having a first region with a first potential and a second region with a second, higher potential, with the second region being offset in depth from the first region in a semiconductor chip. A storage node may be positioned at substantially the same depth as the second region of the photodiode. A storage gate may be operable to transfer charge between the photodiode and the storage node.

Claims

1. An image sensor pixel comprising:

a photosensitive region formed along a surface of a semiconductor chip;

a storage node below and at least partially overlapping with the photosensitive region; and

a second region configured to transfer charge from the photosensitive region to the storage node;

wherein;

the photosensitive region is doped with a first concentration of a dopant; and

the second region is doped with a second concentration of the dopant that is greater than the first concentration.

2. The image sensor pixel of claim 1, wherein the storage node is positioned entirely beneath the photosensitive region.

3. The image sensor pixel of claim 1, further comprising a floating diffusion node configured to receive a charge from the storage node.

4. The image sensor pixel of claim 3, wherein:

the floating diffusion node is coupled to the storage node by a transfer gate that is configured to reset the storage node when activated; and

the storage node is coupled to the photosensitive region by a storage gate operable to selectively transfer charge from the photosensitive region to the storage node.

5. The image sensor pixel of claim 3, wherein:

the surface is a first surface of the semiconductor chip;

the storage node is formed along a second surface of the semiconductor chip opposite to the first surface; and

the floating diffusion node is positioned proximate to the second surface of the semiconductor chip.

6. The image sensor pixel of claim 3, wherein the floating diffusion node is positioned on a separate chip that is distinct from the semiconductor chip.

7. The image sensor pixel of claim 1, further comprising a shielding region configured between the photosensitive region and the storage node.

8. An image sensor comprising:

a photodiode having a photosensitive first region formed along a first surface of a semiconductor chip and a second region formed below a portion of the first region and extending to proximate a second surface opposite to the first surface of the semiconductor chip;

a storage node formed in the semiconductor chip at a depth below and at least partially overlapping with the first region; and

a storage gate coupled to a second surface of the semiconductor chip opposite to the first surface and configured to pump a charge from the second region to the storage node;

wherein;

the first region is doped with a first concentration of a dopant; and

the second region is doped with a second concentration of the dopant, the second concentration being greater than the first concentration.

9. The image sensor of claim 8, wherein the storage gate is configured to selectively increase a potential of the second region in response to an applied voltage.

10. The image sensor of claim 8, wherein a first inherent potential of the first region is approximately equal to a second inherent potential of the second region.

11. The image sensor of claim 8, wherein the storage node is bifurcated into two regions having different levels of doping.

12. The image sensor of claim 8, wherein the surface is a first surface of the semiconductor chip;

and

the storage node is pinned to the second surface.

13. The image sensor of claim 12, wherein:

pinning the storage gate creates a virtual barrier for charge entering from the storage gate until an applied voltage to the storage gate is reduced.

14. The image sensor of claim 8, wherein the second region is not pinned to the second surface of the semiconductor chip.

15. The image sensor of claim 8, wherein:

the storage node is a first storage node;

the depth of the first storage node is a first depth;

the storage gate is first storage gate; and

the image sensor further comprises;

a second storage node formed in the semiconductor chip at a second depth below and at least partially overlapping with the first region; and

a second storage gate positioned on the second surface of the semiconductor chip and configured to pump a charge from the second region to the second storage node.

16. The image sensor of claim 15, wherein the second storage node is located opposite to the first storage node with respect to the second region.

17. An image pixel comprising:

a photodiode having a photosensitive first region positioned along a first surface of a semiconductor chip and a second region positioned below a portion of the first region; and

a storage node positioned proximate to a second surface of the semiconductor chip opposite to the first surface and at least partially overlapping the first region of the photodiode,

wherein the storage node is bifurcated into a first region having a first doping level and a second region having a second doping level that is different than the first doping level.

18. The image pixel of claim 17, wherein the storage node is coupled to the photodiode by a storage gate that is configured to pump a charge from the photodiode to the storage node in response to an applied voltage.

19. The image pixel of claim 17, wherein the bifurcated storage node is pinned to the second surface and forms a virtual barrier that resists charge from entering the storage node until the applied voltage is reduced.

20. The image pixel of claim 17, further comprising:

a floating diffusion node that is configured to receive a charge from the storage node; and

a transfer gate coupling the storage node to the floating diffusion node and configured to reset the storage mode when activated.