Integrated RF front end system

• US 10,263,072 B2
• Filed: 10/30/2017
• Issued: 04/16/2019
• Est. Priority Date: 06/28/2012
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: McPartlin, Michael Joseph, Doherty, Mark M.
• Primary Examiner(s): Nguyen, Tuan H
• Application Number:
  US15/798,129
• Publication Number:
  US 20180130876A1
• Time in Patent Office: 533 Days
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 2223/665 Bias feed arrangements
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/067 Lateral bipolar transistor in combination with diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0823 including vertical bipolar transistors only
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0821 : Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/0826 : Pedestal collectors
• CPC Class Codes: H01L 29/165 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66242 : Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 29/737 : Hetero-junction transistors
• CPC Class Codes: H01L 29/7371 : Vertical transistors
• CPC Class Codes: H01L 29/7378 : comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01Q 1/24 : with receiving set
• CPC Class Codes: H03F 2200/222 : A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/318 : A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/387 : A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/411 : the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/451 : the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/245 : with semiconductor devices only

Abstract

Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

Claims

1. A semiconductor device for an integrated front-end module comprising:

a silicon substrate having a high-resistivity portion;

an active radio frequency device disposed on the substrate above the high-resistivity portion;

a low-resistivity well disposed a first distance away from the active radio frequency device and providing at least partial electrical isolation between the active radio frequency device and a passive device; and

a trench disposed between the active radio frequency device and the low-resistivity well, the trench configured to impede movement across the trench of carriers in the high resistivity portion of the silicon substrate.

2. The semiconductor device of claim 1 wherein the active radio frequency device is a transistor and the low-resistivity well at least partially surrounds a collector of the transistor.

3. The semiconductor device of claim 1 wherein the trench is spaced apart from the active radio frequency device and spaced apart from the low-resistivity well.

4. The semiconductor device of claim 1 wherein the trench is disposed immediately adjacent to the low-resistivity well.

5. The semiconductor device of claim 1 further comprising a low-resistivity epitaxial layer of a different impurity type than an impurity type of the silicon substrate, the low-resistivity epitaxial layer disposed above the silicon substrate.

6. The semiconductor device of claim 1 further comprising a high-resistivity region disposed a second distance from the active radio frequency device and at least partially surrounding the active radio frequency device, the second distance greater than the first distance.

7. The semiconductor device of claim 6 wherein the passive device is disposed directly above the high-resistivity region.

8. The semiconductor device of claim 1 wherein the low-resistivity well at least partially surrounds the active radio frequency device.

9. A wireless device comprising:

a front-end module including a silicon substrate, an active radio frequency device, a low-resistivity well, and a trench, the silicon substrate having a high-resistivity portion, the active radio frequency device disposed on the substrate above the high-resistivity portion, the low-resistivity well disposed a first distance away from the active radio frequency device, the low-resistivity well providing at least partial electrical isolation between the active radio frequency device and a passive device, the trench disposed between the active radio frequency device and the low-resistivity well, and the trench configured to impede movement across the trench of carriers in the high resistivity portion of the silicon substrate; and

an antenna in electrical communication with the front-end module, the antenna configured to receive and transmit wireless signals.

10. The wireless device of claim 9 wherein the active radio frequency device is a transistor and the low-resistivity well at least partially surrounds a collector of the transistor.

11. The wireless device of claim 9 wherein the trench is spaced apart from the active radio frequency device and spaced apart from the low-resistivity well.

12. The wireless device of claim 9 wherein the trench is disposed immediately adjacent to the low-resistivity well.

13. The wireless device of claim 9 wherein the front-end module further includes a low-resistivity epitaxial layer of a different impurity type than an impurity type of the silicon substrate, the low-resistivity epitaxial layer disposed above the silicon substrate.

14. The wireless device of claim 9 wherein the front-end module further includes a high-resistivity region disposed a second distance from the active radio frequency device and at least partially surrounding the active radio frequency device, the second distance greater than the first distance.

15. The wireless device of claim 14 wherein the passive device is disposed directly above the high-resistivity region.

16. A method of fabricating a front-end module, the method comprising:

creating, from a silicon wafer, a silicon substrate having a high-resistivity portion;

disposing an active radio frequency device on the substrate above the high-resistivity portion;

forming a low-resistivity well at least partially around the active radio frequency device and a first distance away from the active radio frequency device, the low-resistivity well providing at least partial electrical isolation between the active radio frequency device and a passive device; and

forming a trench between the active radio frequency device and the low-resistivity well, the trench configured to impede movement across the trench of carriers in the high resistivity portion of the silicon substrate.

17. The method of claim 16 further comprising forming a low-resistivity epitaxial layer of a different impurity type than an impurity type of the silicon substrate.

18. The method of claim 17 wherein forming the low-resistivity epitaxial layer includes causing a low-resistivity material to out-diffuse from a sub-collector region of the silicon substrate and to form on a surface of the silicon substrate.

19. The method of claim 16 further comprising forming a high-resistivity region a second distance from the active radio frequency device that is greater than the first distance, the high-resistivity region at least partially surrounding the active radio frequency device.

20. The method of claim 19 wherein forming the high-resistivity region includes treating a top layer of the silicon substrate with a crystal lattice destroying agent.