III-V semiconductor layers, III-V semiconductor devices and methods of manufacturing thereof

• US 10,263,073 B2
• Filed: 01/03/2017
• Issued: 04/16/2019
• Est. Priority Date: 11/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Van Dal, Mark, Doornbos, Gerben, Passlack, Matthias, Holland, Martin Christopher
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US15/397,508
• Publication Number:
  US 20180151669A1
• Time in Patent Office: 833 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A gate-all-around field effect transistor (GAA FET) includes an InAs nano-wire as a channel layer, a gate dielectric layer wrapping the InAs nano-wire, and a gate electrode metal layer formed on the gate dielectric layer. The InAs nano-wire has first to fourth major surfaces three convex-rounded corner surfaces and one concave-rounded corner surface.

Claims

1. A method of manufacturing a gate-all-around field effect transistor (GAA FET), the method comprising:

forming a shallow-trench-isolation (STI) in a silicon (Si) substrate, the STI surrounding a Si region of the silicon substrate;

recessing the Si region;

after the Si region is recessed, forming a compound semiconductor layer on a surface of the recessed Si region;

forming a Group III-V semiconductor layer on the compound semiconductor layer;

after the Group III-V semiconductor layer is formed, recessing the STI so as to expose a part of the compound semiconductor layer under the Group III-V semiconductor layer;

removing the compound semiconductor layer; and

after the compound semiconductor is removed, forming a gate dielectric layer and a metal gate layer around the Group III-V semiconductor layer.

2. The method of claim 1, further comprising, after the recessing the STI and before the removing the compound semiconductor layer:

forming a dummy dielectric layer on the Group III-V layer;

forming a dummy polysilicon layer on the dummy dielectric layer;

patterning the dummy polysilicon layer, thereby forming a dummy gate;

forming sidewall spacers on opposing side faces of the dummy gate;

after the sidewall spacers are formed, forming a first interlayer dielectric (ILD) layer; and

removing the dummy gate, thereby forming an opening,

wherein the compound semiconductor is removed through the opening.

3. The method of claim 2, wherein the Group III-V semiconductor layer is an InAs layer.

4. The method of claim 3, wherein the compound semiconductor layer is an InP layer.

5. The method of claim 4, wherein the Si substrate has a (100) plane as a principal surface.

6. The method of claim 5, wherein the Si region is recessed by etching with tetramethylammonium hydroxide.

7. The method of claim 6, wherein after the compound semiconductor layer is formed, an upper portion of the compound semiconductor layer has two (111) planes forming a triangular cross section.

8. The method of claim 7, wherein the Group III-V semiconductor layer has first to fourth major surfaces three convex-rounded corner surfaces and one concave-rounded corner surface.

9. The method of claim 8, wherein:

the first convex-rounded corner surface connects the first and second major surfaces,

the concave-rounded corner surface connects the second and third major surfaces,

the second convex-rounded corner surface connects the third and fourth major surfaces, and

the third convex-rounded corner surface connects the fourth and third major surfaces.

10. The method of claim 8, wherein the second and third major surfaces are in contact with the two (111) planes of the compound semiconductor layer, before the compound semiconductor layer is removed.

11. The method of claim 8, wherein:

extended planes of the first and second major surfaces make an acute angle,

extended planes of the second and third major surfaces make an angle of 60°

to 150°

,

extended planes of the third and fourth major surfaces make an acute angle, and

extended planes of the fourth and first major surfaces make an acute angle.

12. The method of claim 11, wherein the extended planes of the second and third major surfaces make an angle of 90°

to 150°

.

13. The method of claim 1, wherein in the removing the compound semiconductor layer, the compound semiconductor layer is partially removed.

14. The method of claim 1, wherein the gate dielectric layer is also formed between the metal gate layer and the recessed Si region.

15. The method of claim 1, wherein a void is formed in the metal gate layer between the III-V semiconductor layer and the recessed Si region.

16. A method of manufacturing a gate-all-around field effect transistor (GAA FET), the method comprising:

forming a shallow-trench-isolation (STI) in a silicon (Si) substrate, the STI surrounding a Si region of the silicon substrate;

recessing the Si region;

after the Si region is recessed, forming a compound semiconductor layer on a surface of the recessed Si region;

after the compound semiconductor layer is formed, planarizing an upper portion of the compound semiconductor layer,

forming a Group III-V semiconductor layer on the planarized compound semiconductor layer;

after the Group III-V semiconductor layer is formed, recessing the STI so as to expose a part of the compound semiconductor layer under the Group III-V semiconductor layer;

removing the compound semiconductor layer; and

forming a gate dielectric layer and a metal gate layer around the Group III-V semiconductor layer.

17. The method of claim 16, further comprising, after the recessing the STI and before the removing the compound semiconductor layer:

forming a dummy dielectric layer on the Group III-V layer;

forming a dummy polysilicon layer on the dummy dielectric layer;

patterning the dummy polysilicon layer, thereby forming a dummy gate;

forming sidewall spacers on opposing side faces of the dummy gate;

after the sidewall spacers are formed, forming a first interlayer dielectric (ILD) layer; and

removing the dummy gate, thereby forming an opening,

wherein the compound semiconductor is removed through the opening.

18. The method of claim 17, wherein:

the Group III-V semiconductor layer is an InAs layer, and

the compound semiconductor layer is an InP layer.

19. The method of claim 18, wherein the Group III-V semiconductor layer has a cross section having a substantially triangular shape with rounded corners.