Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

• US 10,263,087 B2
• Filed: 07/18/2017
• Issued: 04/16/2019
• Est. Priority Date: 05/25/2007
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Levy, Sagy, Jenne, Fredrick, Ramkumar, Krishnaswamy
• Primary Examiner(s): Yushina, Galina G
• Application Number:
  US15/653,102
• Publication Number:
  US 20170352732A1
• Time in Patent Office: 637 Days
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane

Abstract

A memory is described. Generally, the memory includes a number of non-planar multigate transistors, each including a channel of semiconducting material overlying a surface of a substrate and electrically connecting a source and a drain, a tunnel dielectric layer overlying the channel on at least three sides thereof, and a multi-layer charge-trapping region overlying the tunnel dielectric layer. In one embodiment, the multi-layer charge-trapping region includes a first deuterated layer overlying the tunnel dielectric layer and a first nitride-containing layer overlying the first deuterated layer. Other embodiments are also described.

Claims

1. A memory device comprising:

a channel of semiconducting material overlying a surface of a substrate and electrically connecting a source and a drain;

a tunnel dielectric layer surrounding the channel; and

a multi-layer charge-trapping region surrounding the tunnel dielectric layer, the multi-layer charge-trapping region comprising a first deuterated layer overlying the tunnel dielectric layer, a first nitride-containing layer overlying the first deuterated layer, and a second nitride-containing layer overlying the first nitride-containing layer,

wherein the first nitride-containing layer is deuterated and the second nitride-containing layer is deuterium-free, and

wherein the first nitride-containing layer is substantially trap-free and the second nitride-containing layer includes a majority of charge traps distributed in the multi-layer charge-trapping region.

2. The memory device of claim 1, wherein the first deuterated layer comprises a deuterated derivative of a material used to form the first nitride-containing layer, and has a concentration of deuterium greater than the first nitride-containing layer.

3. The memory device of claim 1 wherein the second nitride-containing layer comprises an oxygen-lean nitride layer and the first nitride-containing layer comprises an oxygen-rich nitride layer.

4. The memory device of claim 1 wherein the channel comprises a long axis parallel to the surface of the substrate.

5. The memory device of claim 1 comprising a plurality of memory devices including channels having a long axis parallel to the surface of the substrate in a Bit-Cost Scalable (BiCS) architecture.

6. The memory device of claim 1 wherein the multi-layer charge-trapping region further comprises a second deuterated layer overlying the second nitride-containing layer.

7. The memory device of claim 6 wherein the second deuterated layer has a concentration of deuterium lower than a concentration of deuterium in the first deuterated layer.

8. The memory device of claim 6 wherein the first deuterated layer comprises a first deuterium gradient that decreases from a first deuterium concentration near the tunnel dielectric layer to a second deuterium concentration near the first nitride-containing layer, and the second deuterated layer comprises a second deuterium gradient that increases from a third deuterium concentration near the second nitride-containing layer to a fourth deuterium concentration near a top surface of the second deuterated layer.

9. A memory comprising:

a vertical stack of non-planar memory devices, each non-planar memory device including;

a channel of semiconducting material having a long axis parallel to a surface of a substrate;

a tunnel dielectric layer overlying the channel on all sides thereof; and

a multi-layer charge-trapping region overlying the tunnel dielectric layer, the multi-layer charge-trapping region comprising a first deuterated layer overlying the tunnel dielectric layer, a first nitride-containing layer overlying the first deuterated layer, and a second nitride-containing layer overlying the first nitride-containing layer,

wherein the first nitride-containing layer is deuterated and the second nitride-containing layer is deuterium-free, and

wherein the first nitride-containing layer is substantially trap-free and the second nitride-containing layer includes a majority of charge traps distributed in the multi-layer charge-trapping region.

10. The memory device of claim 9 wherein the multi-layer charge-trapping region further comprises a second deuterated layer overlying the second nitride-containing layer.

11. The memory device of claim 10 wherein the second deuterated layer has a concentration of deuterium lower than a concentration of deuterium in the first deuterated layer.

12. The memory device of claim 10 wherein the first deuterated layer comprises a first deuterium gradient that decreases from a first deuterium concentration near the tunnel dielectric layer to a second deuterium concentration near the first nitride-containing layer, and the second deuterated layer comprises a second deuterium gradient that increases from a third deuterium concentration near the second nitride-containing layer to a fourth deuterium concentration near a top surface of the second deuterated layer.

13. The memory device of claim 9, wherein the first deuterated layer comprises a deuterated derivative of a material used to form the first nitride-containing layer, and has a concentration of deuterium greater than the first nitride-containing layer.

14. A memory comprising:

a vertical stack of non-planar memory devices, each non-planar memory device including;

a channel of semiconducting material having a long axis parallel to a surface of a substrate;

a tunnel dielectric layer surrounding the channel;

a first deuterated layer overlying the tunnel dielectric layer;

a multi-layer charge-trapping region overlying the first deuterated layer, the multi-layer charge-trapping region comprising two or more nitride-containing layers including a first nitride-containing layer proximal to the first deuterated layer, and a second nitride-containing layer overlying the first nitride-containing layer; and

a second deuterated layer overlying the second nitride-containing layer,

wherein the first nitride-containing layer is deuterated and oxygen-rich, and the second nitride-containing layer comprises a deuterium-free, oxygen-lean nitride layer.

15. The memory device of claim 14 wherein the second deuterated layer has a concentration of deuterium lower than a concentration of deuterium in the first deuterated layer.

16. The memory device of claim 14 wherein the first deuterated layer comprises a first deuterium gradient that decreases from a first deuterium concentration near the tunnel dielectric layer to a second deuterium concentration near the first nitride-containing layer, and the second deuterated layer comprises a second deuterium gradient that increases from a third deuterium concentration near the second nitride-containing layer to a fourth deuterium concentration near a top surface of the second deuterated layer.

17. The memory device of claim 14, wherein the first deuterated layer comprises a deuterated derivative of a material used to form the first nitride-containing layer, and has a concentration of deuterium greater than the first nitride-containing layer.