Semiconductor device with deep diffusion region

• US 10,263,101 B2
• Filed: 10/17/2016
• Issued: 04/16/2019
• Est. Priority Date: 10/27/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Wuebben, Thomas, Irsigler, Peter, Schulze, Hans-Joachim
• Primary Examiner(s): Hossain, Moazzam
• Assistant Examiner(s): Isaac, Stanetta D
• Application Number:
  US15/295,109
• Publication Number:
  US 20170117395A1
• Time in Patent Office: 911 Days
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/2252 using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of processing a semiconductor device, comprising: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom; applying a substance onto at least a section of a trench surface formed by one of the trench sidewalls and/or the trench bottom of the at least one trench, such that applying the substance includes preventing that the substance is applied to the other of the trench sidewalls; and diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section.

Claims

1. A method of processing a semiconductor device, comprising:

providing a semiconductor body having dopants of a first conductivity type;

forming a trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom;

applying a substance onto a section of a trench surface of the trench, wherein the section is formed by at least one of a first trench sidewall of the two trench sidewalls and at least a portion of the trench bottom of the trench, and wherein applying the substance includes preventing the substance from being applied to a second sidewall of the two trench sidewalls; and

diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section, wherein the semiconductor region is arranged adjacent to only the first sidewall.

2. The method of claim 1, wherein applying the substance includes at least one of a plasma deposition, a tilt angle implantation, and an implantation along substantially only the vertical direction.

3. The method of claim 1, wherein the substance is gaseous, and applying the substance includes a masked diffusion.

4. The method of claim 1, further comprising, before applying the substance, carrying out a sputtering process for removing an oxide layer present at the section that came into being after forming the trench.

5. The method of claim 1, wherein the substance includes at least one of boron, aluminum and gallium.

6. The method of claim 1, wherein the substance includes at least one of phosphorus, antimony and arsenic.

7. The method of claim 1, wherein a transition between the trench and the created semiconductor region extends continuously along only the first trench sidewall to the trench bottom of the trench.

8. The method of claim 1, wherein semiconductor body is provided as a part of a semiconductor wafer having a diameter of at least 200 mm.

9. The method of claim 1, further comprising:

implanting dopants of the second conductivity type into the semiconductor body by carrying out a surface implantation.

10. The method of claim 1, further comprising, before applying the substance:

creating a masking layer at the trench surface;

filling the trench with a trench filling material;

forming a mask that only partially covers an opening of the trench; and

removing both a share of the trench filling material that is not covered by the mask and a part of the masking layer adjacent to the share so as to expose only the section of the trench surface that is subjected to a subsequent application of the substance.

11. The method of claim 10, further comprising, after applying the substance:

removing both a remaining share of the trench filling material and a remaining masking layer within the trench, and, subsequently, diffusing the applied substance from the section into the semiconductor body.

12. The method of claim 1, further including:

forming a control electrode within the trench.

13. The method of claim 1, wherein applying the substance and diffusing the applied substance are carried out such that a dopant concentration of the created semiconductor region adjacent to the first trench sidewall amounts to a value that is within a range of 50% to 150% of a fixed dopant concentration value at any point along at least 60% of a total extension of the semiconductor region in the vertical direction.

14. The method of claim 1, wherein applying the substance and diffusing the applied substance are carried out such that a dopant concentration of the semiconductor region adjacent to the first trench sidewall changes, in a portion amounting to at least 80% of a total extension of the semiconductor region in the vertical direction, by at least 30% from a dopant concentration value being present in the portion of the total extension.