Method and apparatus for adapting a variable impedance network

• US 10,263,595 B2
• Filed: 08/10/2017
• Issued: 04/16/2019
• Est. Priority Date: 03/22/2010
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Blackberry Limited
• Inventors: Manssen, Keith, Greene, Matthew Russell
• Primary Examiner(s): Jones, Stephen E.
• Application Number:
  US15/673,613
• Publication Number:
  US 20170373661A1
• Time in Patent Office: 614 Days
• Field of Search: 333 32, 333 33, 333 173
• CPC Class Codes: H03H 5/12 with at least one voltage- or current-dependent element
• CPC Class Codes: H03H 7/004 Capacitive coupling circuits not otherwise provided for
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H03H 7/40 Automatic matching of load impedance to source impedance
• CPC Class Codes: H03K 17/56 by the use, as active elements, of semiconductor devices using diodes H03K17/74

Abstract

The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

Claims

1. A device comprising:

a tunable array of switched capacitors comprising a plurality of capacitors coupled to a plurality of switches, each of the plurality of capacitors having a fixed capacitance value, each of the plurality of switches having a resistance associated therewith;

wherein the capacitance values of the plurality of capacitors comprise a non-binary array, and

wherein the array of switched capacitors is adapted to have non-uniform quality (Q) factors.

2. The device of claim 1, wherein each combination of a capacitor of the plurality of capacitors and a switch of the plurality of switches has a quality (Q) factor, and the array corresponds to a plurality of combinations having different Q factors.

3. The device of claim 1, wherein a first capacitor and a second capacitor of the array of switched capacitors each have a capacitance value equal to a largest capacitance value of the non-binary array.

4. The device of claim 1,

wherein the device comprises a matching network operating in a frequency range having a low-frequency portion and a high-frequency portion,

wherein a first capacitor having a capacitance value equal to a largest capacitance value of the array is connected to a first resistance of a first switch to maintain a target quality (Q) factor for the matching network while operating in the low-frequency portion of the frequency range, and is not connected to the first resistance while the matching network is operating in the high-frequency portion of the frequency range.

5. The device of claim 1, wherein at least a portion of the array of switched capacitors is contained on a die.

6. The device of claim 1, wherein the resistance associated with at least one switch of the plurality of switches comprises a parasitic resistance.

7. The device of claim 1, wherein at least one switch of the plurality of switches comprises a semiconductor switch.

8. The device of claim 1, wherein at least one switch of the plurality of switches comprises a micro-electro-mechanical systems (MEMS) switch.

9. A device comprising:

a tunable array of switched capacitors comprising a plurality of capacitors coupled to a plurality of switches, each of the plurality of capacitors having a fixed capacitance value, each of the plurality of switches having a resistance associated therewith,

wherein the array of switched capacitors is adapted to have non-uniform quality (Q) factors, the array of switched capacitors thereby adapted to maintain a Q factor for the array over a predetermined portion of a frequency range of the device.

10. The device of claim 9, wherein each combination of a capacitor of the plurality of capacitors and a switch of the plurality of switches has a Q factor, and the array corresponds to a plurality of combinations having different Q factors.

11. The device of claim 9,

wherein the device comprises a matching network operating in the frequency range, the frequency range having a low-frequency portion and a high-frequency portion,

wherein a first capacitor having a capacitance value equal to a largest capacitance value of the array is connected to a first resistance of a first switch to maintain a target quality (Q) factor for the matching network while operating in the low-frequency portion of the frequency range, and is not connected to the first resistance while the matching network is operating in the high-frequency portion of the frequency range.

12. The device of claim 9, wherein at least a portion of the array of switched capacitors is contained on a die.

13. The device of claim 9, wherein the resistance associated with at least one switch of the plurality of switches comprises a parasitic resistance.

14. The device of claim 9, wherein at least one switch of the plurality of switches comprises a semiconductor switch.

15. The device of claim 9, wherein at least one switch of the plurality of switches comprises a micro-electro-mechanical systems (MEMS) switch.

16. A device comprising:

a tunable array of switched reactive elements comprising a plurality of reactive elements coupled to a plurality of switches, each of the plurality of reactive elements having a fixed reactance value, each of the plurality of switches having a resistance associated therewith,

wherein the array of switched reactive elements is adapted to have non-uniform quality (Q) factors, the array of switched reactive elements thereby adapted to maintain a Q factor for the array over a predetermined portion of a frequency range of the device.

17. The device of claim 16, wherein at least one switch of the plurality of switches comprises a semiconductor switch.

18. The device of claim 16, wherein at least one switch of the plurality of switches comprises a micro-electro-mechanical systems (MEMS) switch.

19. The device of claim 16, wherein the array comprises a plurality of capacitors coupled to the plurality of switches, wherein each of the plurality of switches has a parasitic capacitance, and wherein the resistance associated with at least one switch of the plurality of switches comprises a parasitic resistance.

20. The device of claim 19,

wherein the device comprises a matching network operating in the frequency range, the frequency range having a low-frequency portion and a high-frequency portion,

wherein a first capacitor having a capacitance value equal to a largest capacitance value of the plurality of capacitors is connected to a first resistance of a first switch to maintain a target Q factor for the matching network while operating in the low-frequency portion of the frequency range, and is not connected to the first resistance while the matching network is operating in the high-frequency portion of the frequency range.