Level shifter with improved voltage difference

• US 10,263,621 B2
• Filed: 03/24/2017
• Issued: 04/16/2019
• Est. Priority Date: 03/24/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Shang-Chi, Cheng, Chiting, Hsieh, Wei-jer, Lin, Yangsyu
• Primary Examiner(s): Wells, Kenneth B
• Application Number:
  US15/468,296
• Publication Number:
  US 20180278252A1
• Time in Patent Office: 753 Days
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A level shifter that comprises an input operating in an input voltage domain and an output for outputting an output signal in an output voltage domain. The level shifter further includes an inverter circuit operating in the input voltage domain for inverting an input signal to create an inverted input signal. The level shifter also includes an intermediate circuit operating in an intermediate voltage domain for generating an intermediate signal. An output buffer circuit generates the output signal based at least in part on the inverted input signal and the intermediate signal.

Claims

1. A level shifter comprising:

an input operating in an input voltage domain;

an inverter circuit operating in the input voltage domain for inverting an input signal to create an inverted input signal in the input voltage domain;

an intermediate circuit operating in an intermediate voltage domain for generating an intermediate signal in the intermediate voltage domain, wherein the input and the inverted input signals are inputs to the intermediate circuit;

an output buffer circuit operating in an output voltage domain and exclusive of the input voltage domain for generating an output signal based at least in part on the inverted input signal and the intermediate signal, wherein the inverted input signal and the intermediate signal are inputs to the output buffer circuit; and

an output for outputting an output signal in the output voltage domain.

2. The level shifter of claim 1, wherein the intermediate circuit comprises two pull-low NMOS transistors, two cross-coupling PMOS transistors, and stacking PMOS transistors between the two pull-low NMOS transistors and the two cross-coupling PMOS transistors.

3. The level shifter of claim 1, wherein the output buffer circuit comprises two stacking PMOS transistors and an NMOS transistor.

4. The level shifter of claim 1, wherein the output buffer circuit comprises two inputs and the intermediate signal is applied to one input and the inverted input signal is applied to the other input.

5. The level shifter of claim 1, wherein an input voltage is applied to the inverter circuit, an intermediate voltage is applied to the intermediate circuit, and an output voltage is applied to the output buffer circuit.

6. The level shifter of claim 5, wherein the input voltage is equal to, less than, or greater than the output voltage.

7. The level shifter of claim 5, wherein the intermediate voltage is less than the output voltage and more than the input voltage.

8. The level shifter of claim 5, wherein the intermediate voltage is created by applying a voltage drop to the output voltage.

9. The level shifter of claim 8, wherein the voltage drop is generated by a MOS transistor configured as a diode.

10. The level shifter of claim 1, wherein there is a two gate delay from the input to the output when the input goes from a logical low value to a logical high value.

11. The level shifter of claim 1, wherein an aggregate gate delay for the level shifter is less than a 3 gate delay.

12. A level shifter comprising:

an inverter circuit operating in an input voltage domain for inverting an input signal to create an inverted input signal in the input voltage domain;

an intermediate circuit for receiving the input signal and generating an intermediate signal in an intermediate voltage domain, the intermediate circuit comprising two pull-low NMOS transistors, two cross-coupling PMOS transistors, and stacking PMOS transistors between the pull-low NMOS transistors and the cross coupling PMOS transistors, wherein the input signal and the inverted input signals are inputs to the intermediate circuit; and

an output buffer circuit operating in an output voltage domain and exclusive of the input voltage domain for generating an output signal in the output voltage domain based at least in part on the inverted input signal and the intermediate signal, the output buffer signal comprising at least two inputs, two stacking PMOS transistors, and an NMOS transistor, wherein the inverted input signal and the intermediate signal are inputs to the output buffer circuit.

13. The level shifter of claim 12, wherein the output buffer circuit comprises two inputs and the intermediate signal is applied to one input and the inverted input signal is applied to the other input.

14. The level shifter of claim 12, wherein an input voltage is applied to the inverter circuit, an intermediate voltage is applied to the intermediate circuit, and an output voltage is applied to the output buffer circuit.

15. The level shifter of claim 14, wherein the input voltage is equal to, less than, or greater than the output voltage.

16. The level shifter of claim 14, wherein the intermediate voltage is equal to, less than, or greater than the output voltage and more than the input voltage.

17. The level shifter of claim 14, wherein the intermediate voltage is created by reducing the output voltage with a voltage drop circuit.

18. The level shifter of claim 17, wherein the voltage drop is generated by a MOS transistor configured as a diode.

19. The level shifter of claim 12, wherein an aggregate gate delay for the level shifter is less than a 3 gate delay.

20. A method for operating a level shifter comprising:

receiving an input signal in an input voltage domain;

generating a first intermediate signal in the input voltage domain by inverting the input signal;

generating a second intermediate signal in an intermediate voltage domain, wherein the input signal and the first intermediate signal are inputs to a circuit for generating the second intermediate signal in the intermediate voltage domain; and

generating an output signal in an output voltage domain based at least in part on the first intermediate signal and the second intermediate signal, wherein the first intermediate signal and the second intermediate signal are inputs to a circuit operating in the output voltage domain and exclusive of the input voltage domain for generating the output signal in the output voltage domain.