Method of electrically interconnecting circuit assemblies

• US 10,264,664 B1
• Filed: 06/04/2015
• Issued: 04/16/2019
• Est. Priority Date: 06/04/2015
• Status: Active Grant

• Current Assignee: Vicor Corporation
• Original Assignee: VLT Incorporated (Vicor Corporation)
• Inventors: Vinciarelli, Patrizio, Lavery, Patrick R., Mutter, Rudolph F., Kirk, Jeffery J., D'Amico, Andrew T.
• Primary Examiner(s): Arbes, Carl J
• Application Number:
  US14/731,287
• Time in Patent Office: 1,412 Days
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 23/053 the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/28 Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H05K 1/0204 using means for thermal conduction connection in the thickness direction of the substrate H05K1/0207 takes precedence
• CPC Class Codes: H05K 1/111 Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 1/186 manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 2201/049 PCB for one component, e.g. for mounting onto mother PCB
• CPC Class Codes: H05K 2201/09181 Notches in edge pads
• CPC Class Codes: H05K 2201/1003 Non-printed inductor
• CPC Class Codes: H05K 2201/10515 Stacked components
• CPC Class Codes: H05K 3/0014 Shaping of the substrate, e.g. by moulding
• CPC Class Codes: H05K 3/0026 by laser ablation
• CPC Class Codes: H05K 3/0044 Mechanical working of the substrate, e.g. drilling or punching H05K3/0008 takes precedence
• CPC Class Codes: H05K 3/0052 Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/0079 characterised by the method of application or removal of the mask H05K3/0091 takes precedence
• CPC Class Codes: H05K 3/16 by cathodic sputtering
• CPC Class Codes: H05K 3/18 using precipitation techniques to apply the conductive material
• CPC Class Codes: H05K 3/207 : using a prefabricated paste pattern, ink pattern or powder pattern
• CPC Class Codes: H05K 3/24 : Reinforcing the conductive pattern by solder coating H05K3/3457
• CPC Class Codes: H05K 3/3442 : having edge contacts, e.g. leadless chip capacitors, chip carriers
• CPC Class Codes: H05K 3/381 : by special treatment of the substrate
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence
• CPC Class Codes: H05K 3/4638 : Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.

Abstract

Electronic modules having complex contact structures may be formed by encapsulating panels containing pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within the panel along the cut lines. Holes defining contact regions along the electronic module sidewall may be cut into the panel along the cut lines to expose the buried interconnects. The panel may be metallized, e.g. by a series or processes including plating, on selected surfaces including in the holes to form the contacts and other metal structures followed by cutting the panel along the cut lines to singulate the individual electronic models. The contacts may be located in a conductive grove providing a castellated module.

Claims

1. A method of electrically interconnecting circuit assemblies, the method comprising:

assembling an encapsulated panel including a printed circuit board having electronic components mounted to the printed circuit board and one or more conductive features enclosed within the panel and unexposed to an exterior surface of the panel, the encapsulated panel comprising one or more electronic modules having boundaries defined by one or more predetermined cut lines, and the one or more conductive features having portions that are located along the cut lines and unexposed to an exterior surface of the panel;

selectively forming holes in the panel at predetermined locations along the cut lines exposing within selected holes respective portions of the one or more conductive features;

selectively forming one or more conductive metal layers on selected surfaces of the panel including along sidewalls within the selected holes, each selected hole having a respective portion of the one or more conductive metal layers along sidewalls within the selected holes being in electrical contact with the respective portions of the one or more conductive features; and

cutting the panel through the holes and along the one or more cut lines singulating the one or more electronic modules, leaving each singulated electronic module with electrical contacts that include portions of the sidewalls of the selected holes along a perimeter edge of the module.

2. The method of claim 1, further comprising preparing one or more surfaces of the encapsulated panel.

3. The method of claim 2 wherein the preparing one or more surfaces comprises lapping the panel before selectively forming the holes.

4. The method of claim 2 wherein the preparing one or more surfaces comprises lapping the panel after selectively forming the holes.

5. The method of claim 2 wherein the preparing one or more surfaces comprises cleaning the panel ultrasonically in an aqueous solution before selectively forming the one or more metal layers.

6. The method of claim 2 wherein the preparing one or more surfaces comprises laser etching the panel before selectively forming the one or more metal layers.

7. The method of claim 2 wherein the selectively forming one or more conductive metal layers further comprises:

(a) applying a seed layer including conductive particles to the surfaces of the panel, and subsequently (b) plating a layer of metal onto the seed layer.

8. The method of claim 7 wherein applying the seed layer comprises sputter coating the encapsulated panel with conductive particles.

9. The method of claim 8 wherein the sputtering comprises sputtering copper particles.

10. The method of claim 9 wherein the sputtering further comprises sputtering chromium particles.

11. The method of claim 10 further comprising coating the encapsulated panel with colloidal graphite and curing the graphite before the plating.

12. The method of claim 10 further comprising patterning the metal before cutting the panel.

13. The method of claim 12 wherein the patterning comprises masking and subsequently etching the metal layer.

14. The method of claim 13 wherein the patterning further comprises using a laser to expose or remove portions of the mask.

15. The method of claim 12 further comprising applying one or more finishing layers on top of the metal layer.

16. The method of claim 7 wherein applying the seed layer comprises applying conductive epoxy.

17. The method of claim 16 wherein applying the seed layer further comprises applying the conductive epoxy in a predetermined pattern.

18. The method of claim 17 further comprising coating the encapsulated panel with colloidal graphite and curing the graphite before the plating.

19. The method of claim 17 further comprising applying one or more finishing layers on top of the metal layer.

20. The method of claim 1 further comprising configuring the holes to provide gaps between adjacent contacts;

and

wherein the holes establish a pattern in the conductive metal layers along the perimeter edge of the one or more electronic modules.

21. The method of claim 1 further comprising patterning the one or more metal layers to form conductive pads on a selected surface of the one or more electronic modules, the pads providing a surface mounting area for one or more components.

22. The method of claim 21 wherein patterning the metal layer further comprises establishing electrical connections between respective ones of the pads to respective ones of the electrical contacts.

23. The method of claim 1 further comprising:

selectively forming auxiliary holes in the panel at predetermined locations spaced away from the cut lines; and

selectively forming one or more conductive metal layers within the auxiliary holes to form thermal conduits for conducting heat from respective interior portions of the one or more electronic modules to an exterior surface.

24. The method of claim 23 wherein the auxiliary holes are cut to a controlled depth without exposing within the auxiliary holes any components in the one or more electronic modules.

25. The method of claim 24 wherein the auxiliary holes are cut through the entire thickness of the panel without exposing within the auxiliary holes any components in the one or more electronic modules.

26. The method of claim 25 wherein the cutting auxiliary holes exposes within selected ones of the auxiliary holes respective portions of one or more auxiliary conductive features.

27. The method of claim 1 further comprising:

selectively forming auxiliary holes in the panel at predetermined locations spaced away from the cut lines exposing within selected ones of the auxiliary holes respective portions of one or more auxiliary conductive features;

selectively forming one or more conductive metal layers within the auxiliary holes to form electrical connections to the auxiliary conductive features; and

patterning the one or more metal layers to form conductive pads on a selected surface of the one or more electronic modules and electrical connections between selected ones of the pads and the one or more auxiliary conductive features, the pads providing a surface mounting area for one or more components.

28. The method of claim 1 further comprising:

selectively forming auxiliary holes in the panel at predetermined locations spaced away from the cut lines; and

selectively forming one or more conductive metal layers within the auxiliary holes of the one or more electronic modules to an exterior surface.

29. The method of claim 28 wherein the auxiliary holes are cut to a controlled depth in the one or more electronic modules.

30. The method of claim 29 wherein the cutting auxiliary holes exposes within selected ones of the auxiliary holes respective portions of one or more auxiliary conductive features.

31. The method of claim 30 further comprising forming a pad on the exterior surface adjacent one or more of the auxiliary holes and wherein the one or more conductive layers in the one or more auxiliary holes forms an electrical connection between the respective portions of the one or more auxiliary conductive features and the pad.

32. The method of claim 28 wherein the auxiliary holes are cut through the entire thickness of the panel in the one or more electronic modules.

33. The method of claim 32 wherein the cutting auxiliary holes exposes within selected ones of the auxiliary holes respective portions of one or more auxiliary conductive features.

34. The method of claim 33 further comprising forming a pad on the exterior surface adjacent one or more of the auxiliary holes and wherein the one or more conductive layers in the one or more auxiliary holes forms an electrical connection between the respective portions of the one or more auxiliary conductive features and the pad.

35. The method of claim 1 further comprising:

selectively forming auxiliary holes in the panel at predetermined locations spaced away from the cut lines exposing within selected ones of the auxiliary holes respective portions of one or more auxiliary conductive features;

selectively forming one or more conductive metal layers within the auxiliary holes to form electrical connections to the auxiliary conductive features; and

patterning the one or more metal layers to form conductive pads on a selected surface of the one or more electronic modules and electrical connections between selected ones of the pads and the one or more auxiliary conductive features, the pads providing an electrical connection to the one or more auxiliary conductive features.