System and method to diagnose integrated circuit

• US 10,267,853 B2
• Filed: 04/25/2016
• Issued: 04/23/2019
• Est. Priority Date: 12/18/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Changchien, Wei-Pin, Cheng, Hong-Chen, Lin, Pei-Ying, Hsu, Hsin-Wu
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US15/137,833
• Publication Number:
  US 20170176525A1
• Time in Patent Office: 1,093 Days
• CPC Class Codes: G01R 31/308 using non-ionising electromagnetic radiation, e.g. optical radiation investigating or analysing materials by the use of optical means G01N21/00; image analysis G06T7/00
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06T 2207/10061 from scanning electron microscope
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/001 using an image reference approach

Abstract

A diagnostic system includes a location extractor, a file generator, and a chip diagnostic tool. The location extractor is arranged to extract at least a coordinate of at least one component in an intellectual property design layout of an integrated circuit design layout according to at least one tagging text labeling the at least one component in the intellectual property design layout. The file generator is arranged to generate a format file according to the at least coordinate. The chip diagnostic tool is arranged to scan a physical intellectual property circuit in a physical integrated circuit to determine a defect component in the physical intellectual property circuit according to the format file. The physical intellectual property circuit corresponds to the intellectual property design layout, and the physical integrated circuit corresponds to the integrated circuit design layout.

Claims

1. A diagnostic system, comprising:

a processor, arranged to extract at least a coordinate of at least one scan component in a design layout of an integrated circuit (IC) design layout according to at least one tagging text labeling the at least one scan component in the design layout,

and arranged to generate a design exchange format file of the IC design layout according to the at least coordinate; and

a chip diagnostic tool, having a testing platform, the chip diagnostic tool arranged to scan a physical circuit in a physical IC on the testing platform to determine a defect component in the physical circuit according to the design exchange format file;

wherein the physical circuit corresponds to the design layout, and the physical IC corresponds to the IC design layout, the at least one scan component comprises a plurality of scan components, the at least on tagging text comprises a plurality of tagging texts, the processor names the plurality of tagging texts based on a predetermined scanning sequence, and the chip diagnostic tool scans the plurality of scan components in the physical circuit by following the predetermined scanning sequence to determine the defect component in the physical circuit according to the design exchange format file.

2. The diagnostic system of claim 1, wherein the design exchange format file comprises the at least coordinate of the at least one scan component in the design layout.

3. The diagnostic system of claim 1, wherein the chip diagnostic tool further tests the physical IC to determine if the physical circuit has a predetermined functionality, if the predetermined functionality of the physical circuit fails, the chip diagnostic tool scans the physical circuit to determine a defect component in the physical circuit according to the design exchange format file.

4. The diagnostic system of claim 3, wherein the chip diagnostic tool further determines a coordinate of the defect component in the physical circuit according to the design exchange format file.

5. The diagnostic system of claim 1, wherein the at least one scan component is designed for testing of the physical circuit.

6. The diagnostic system of claim 5, wherein the IC design layout comprises a plurality of pins conducting to the plurality of scan components respectively, and the plurality of tagging texts are tagged on the plurality of pins respectively.

7. A method performed upon an integrated circuit (IC) design layout, the method comprising:

placing a design layout to a predetermined location of the IC design layout, wherein the design layout comprises at least one tagging text labeling at least one scan component of the design layout;

determining at least one coordinate of the at least one scan component according to the at least one tagging text;

generating a design exchange format file corresponding to the IC design layout according to the at least one coordinate; and

causing a physical circuit to be fabricated according to the IC design layout;

wherein the at least one tagging text comprises a plurality of tagging texts, the at least one scan component comprises a plurality of scan components, the at least one coordinate comprises a plurality of coordinates, and the plurality of tagging texts label the plurality of scan components respectively, and the method further comprises;

sorting the plurality of coordinates of the plurality of scan components to generate a plurality of sorted coordinates according to a predetermined scanning sequence of the plurality of scan components; and

generating the design exchange format file according to the plurality of sorted coordinates.

8. The method of claim 7, wherein the design exchange format (DEF) file is recognized by a chip diagnostic tool.

9. The method of claim 7, wherein the at least one scan component is designed for testing of the design layout.

10. The method of claim 7, further comprising:

providing a graphic database system (GDS) file corresponding to the design layout;

wherein the at least one tagging text is included in the GDS file.

11. The method of claim 7, wherein generating the design exchange format file corresponding to the IC design layout according to the at least one coordinate comprises:

generating the design exchange format file corresponding to the IC design layout according to the at least one coordinate and at least one functional information of the at least one scan component.

12. The method of claim 7, wherein the IC design layout comprises a plurality of pins conducting to the plurality of scan components respectively.

13. The method of claim 12, wherein the plurality of tagging texts are tagged on the plurality of pins respectively.

14. A method performed upon a physical integrated circuit (IC), the method comprising:

causing the physical circuit to be fabricated according to an IC design layout;

providing the physical IC comprising a physical circuit;

providing a design exchange format file corresponding to the physical IC according to at least one coordinate of at least one scan component having at least one tagging text in the IC design layout;

testing the physical IC to determine if the physical circuit has a predetermined functionality;

if the predetermined functionality of the physical circuit fails, scanning the physical circuit to determine a defect component in the physical circuit according to the design exchange format file;

wherein the at least one scan component comprises a plurality of scan components, the at least one tagging text comprises a plurality of tagging texts, the plurality of tagging texts are named based on a predetermined scanning sequence, and scanning the physical circuit to determine the defect component in the physical circuit according to the design exchange format file comprises;

scanning the plurality of scan components in the physical circuit by following the predetermined scanning sequence to determine the defect component in the physical circuit according to the design exchange format file.

15. The method of claim 14, wherein scanning the physical circuit to determine the defect component in the physical circuit according to the design exchange format file further comprises:

determining a coordinate of the defect component in the physical circuit according to the design exchange format file.

16. The method of claim 14, wherein scanning the physical circuit to determine the defect component in the physical circuit according to the design exchange format file comprises:

using a chip diagnostic tool to scan the physical circuit to determine the defect component in the physical circuit according to the design exchange format file;

wherein the design exchange format file is recognized by the chip diagnostic tool.

17. The method of claim 14, wherein the design exchange format file comprises the at least coordinate of the at least one scan component in the design layout.

18. The method of claim 14, wherein scanning the physical circuit to determine the defect component in the physical circuit according to the design exchange format file comprises:

scanning at least one scan component of the physical circuit to determine the defect component in the physical circuit according to the design exchange format file.

19. The method of claim 18, wherein the at least one scan component is designed for testing of the physical circuit.

20. The method of claim 19, wherein the IC design layout comprises a plurality of pins conducting to the plurality of scan components respectively, and the plurality of tagging texts are tagged on the plurality of pins respectively.