Methods and apparatus for managing power with an inter-processor communication link between independently operable processors
First Claim
1. Integrated circuit apparatus comprising:
- a host processor apparatus;
an auxiliary processor apparatus; and
a shared memory interface comprising a data storage device, the shared memory interface in data communication with each of the host processor apparatus and the auxiliary processor apparatus, the shared memory interface configured to provide an inter-processor communication link configured to enable data transfers between the host processor apparatus and the auxiliary processor apparatus;
wherein the host processor apparatus is configured to transact a data structure to the auxiliary processor apparatus via the inter-processor communication link; and
wherein the data structure is configured to enable one or more of the host processor apparatus and the auxiliary processor apparatus to enter a sleep state.
0 Assignments
0 Petitions
Accused Products
Abstract
Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
-
Citations
20 Claims
-
1. Integrated circuit apparatus comprising:
-
a host processor apparatus; an auxiliary processor apparatus; and a shared memory interface comprising a data storage device, the shared memory interface in data communication with each of the host processor apparatus and the auxiliary processor apparatus, the shared memory interface configured to provide an inter-processor communication link configured to enable data transfers between the host processor apparatus and the auxiliary processor apparatus; wherein the host processor apparatus is configured to transact a data structure to the auxiliary processor apparatus via the inter-processor communication link; and wherein the data structure is configured to enable one or more of the host processor apparatus and the auxiliary processor apparatus to enter a sleep state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A portable device comprising:
-
a first processor apparatus; a second processor apparatus; and a memory interface shared between the first processor apparatus and the second processor apparatus, the memory interface configured to enable data communication between the first processor apparatus and the second processor apparatus via an inter-processor communication link; and a wireless interface associated with the second processor apparatus; wherein the first processor apparatus is configured to transmit a data structure to the second processor apparatus via the inter-processor communication link, the data structure being configured to enable either or both of the first processor apparatus or the second processor apparatus to enter a sleep state. - View Dependent Claims (10, 11, 12, 13, 14)
-
-
15. A non-transitory computer-readable storage medium having instructions stored thereon, the instructions being configured to, when executed by a first processor apparatus, cause the first processor apparatus to:
-
transact a data structure to a second processor apparatus via a shared memory interface, the shared memory interface being configured to enable data communication between the first processor apparatus and the second processor apparatus via an inter-processor communication link; and enable, via the transaction of the data structure, one or more of the first processor apparatus and the second processor apparatus to enter a sleep state. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification