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Methods and apparatus for managing power with an inter-processor communication link between independently operable processors

  • US 10,268,261 B2
  • Filed: 03/30/2018
  • Issued: 04/23/2019
  • Est. Priority Date: 10/08/2014
  • Status: Active Grant
First Claim
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1. Integrated circuit apparatus comprising:

  • a host processor apparatus;

    an auxiliary processor apparatus; and

    a shared memory interface comprising a data storage device, the shared memory interface in data communication with each of the host processor apparatus and the auxiliary processor apparatus, the shared memory interface configured to provide an inter-processor communication link configured to enable data transfers between the host processor apparatus and the auxiliary processor apparatus;

    wherein the host processor apparatus is configured to transact a data structure to the auxiliary processor apparatus via the inter-processor communication link; and

    wherein the data structure is configured to enable one or more of the host processor apparatus and the auxiliary processor apparatus to enter a sleep state.

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