Energy-focused compiler-assisted branch prediction

• US 10,268,480 B2
• Filed: 06/12/2017
• Issued: 04/23/2019
• Est. Priority Date: 02/04/2004
• Status: Active Grant

• Current Assignee: III Holdings 2, LLC
• Original Assignee: III Holdings 2, LLC
• Inventors: Chheda, Saurabh, Carver, Kristopher, Ashok, Raksit
• Primary Examiner(s): Lee, Marina
• Application Number:
  US15/620,468
• Publication Number:
  US 20180107485A1
• Time in Patent Office: 680 Days
• Field of Search: 717130, 717151, 717158
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3846 using static prediction, e.g. branch taken strategy
• CPC Class Codes: G06F 9/3848 using hybrid branch prediction, e.g. selection between prediction techniques

Abstract

A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency.

Claims

1. A memory device having instructions stored thereon that, in response to execution by a processor, cause the processor to perform operations to:

access control information of an instruction sequence at runtime, the control information added in the instruction sequence prior to runtime to prevent coded information corresponding to a control-flow changing instruction from being decoded in a processor pipeline at runtime; and

use the control information to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and to fetch an instruction corresponding to the path.

2. The memory device of claim 1, wherein the control information comprises part of a payload of a coprocessor instruction.

3. The memory device of claim 1, wherein the control information comprises code to select a dynamic branch prediction mechanism.

4. The memory device of claim 1, wherein the control information is configured to stall fetching until another control-flow changing instruction is executed that is not predictable statically or dynamically.

5. The memory device of claim 1, wherein the control information comprises static information that suggests at least one of plural dynamic prediction mechanisms.

6. The memory device of claim 1, wherein the control information specifies a condition under which a control-flow change at an end of the instruction sequence should occur.

7. The memory device of claim 1, wherein the control information comprises part of an instruction configured to affect at least one of processor efficiency or processor energy consumption.

8. A memory device having instructions stored thereon that, in response to execution by a processor, cause the processor to perform operations to:

with respect to an instruction sequence including a control-flow changing instruction to affect a control-flow of the instruction sequence to which control information has been added, removing the control-flow changing instruction from the instruction sequence;

wherein the control information is to be utilized at runtime to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and to fetch an instruction corresponding to the path.

9. The memory device of claim 8, wherein the control information comprises part of an instruction configured to affect at least one of processor efficiency or processor energy consumption.

10. The memory device of claim 8, wherein the control information comprises part of a payload of a coprocessor instruction.

11. The memory device of claim 8, wherein the control information includes static instructions, and wherein the processor is configured to remove the static instructions from a prefetch buffer at runtime to prevent the static instructions from entering a processor pipeline.

12. The memory device of claim 8, wherein the control information comprises code to select a dynamic branch prediction mechanism at runtime.

13. The memory device of claim 8, wherein the control information comprises static information that suggests at least one of plural dynamic prediction mechanisms.

14. A non-transitory computer readable medium, comprising:

an instruction sequence executable by at least one processor, wherein the instruction sequence comprises;

control information to prevent coded information corresponding to a control-flow changing instruction from being decoded in a processor pipeline at runtime in response to execution of the instruction sequence by the at least one processor;

wherein the control information is executable by the at least one processor to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and to fetch an instruction corresponding to the path.

15. The non-transitory computer readable medium of claim 14, wherein the control information comprises part of a payload of a coprocessor instruction.

16. The non-transitory computer readable medium of claim 14, wherein the control information comprises code to select a dynamic branch prediction mechanism.

17. The non-transitory computer readable medium of claim 14, wherein the control information is configured to stall fetching until another control-flow changing instruction is executed that is not predictable statically or dynamically.

18. The non-transitory computer readable medium of claim 14, wherein the control information comprises static information that suggests at least one of plural dynamic prediction mechanisms.

19. The non-transitory computer readable medium of claim 14, wherein the control information specifies a condition under which a control-flow change at an end of the instruction sequence should occur.

20. The non-transitory computer readable medium of claim 14, wherein the control information comprises part of an instruction configured to affect at least one of processor efficiency or processor energy consumption.