Data preservation and recovery in a memory component
First Claim
Patent Images
1. An apparatus, comprising:
- a memory component, the memory component including a bitcell array and a memory controller configured to control memory read and memory write operations directed to the bitcell array, the memory controller including a cache register, a write data register, and a backup register, the memory controller further including;
write logic configured to write a first set of write data to the bitcell array from the write data register, and to cache a second set of write data in a cache register;
data preservation logic configured to transfer the first set of write data from the write data register to a backup data register to preserve the first set of write data in event of a failure to successfully write the first set of write data to the bitcell array wherein the write logic is further configured to copy the second set of write data from the cache register to the write data register after the first set of write data is transferred to the backup register, the data preservation logic being further configured to preserve the second set of write data in the cache register; and
data recovery logic of the memory controller configured to determine whether the first set of write data was successfully written to the bitcell array, and in response to a determination that writing the first set of write data to the bitcell array failed, output the first set of write data preserved in the backup data register.
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Abstract
In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.
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Citations
22 Claims
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1. An apparatus, comprising:
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a memory component, the memory component including a bitcell array and a memory controller configured to control memory read and memory write operations directed to the bitcell array, the memory controller including a cache register, a write data register, and a backup register, the memory controller further including; write logic configured to write a first set of write data to the bitcell array from the write data register, and to cache a second set of write data in a cache register; data preservation logic configured to transfer the first set of write data from the write data register to a backup data register to preserve the first set of write data in event of a failure to successfully write the first set of write data to the bitcell array wherein the write logic is further configured to copy the second set of write data from the cache register to the write data register after the first set of write data is transferred to the backup register, the data preservation logic being further configured to preserve the second set of write data in the cache register; and data recovery logic of the memory controller configured to determine whether the first set of write data was successfully written to the bitcell array, and in response to a determination that writing the first set of write data to the bitcell array failed, output the first set of write data preserved in the backup data register. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method, comprising:
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write logic of a memory controller of a memory component writing a first set of write data to a bitcell array of the memory component from a write data register; the write logic caching a second set of write data in a cache register; data preservation logic of the memory controller transferring the first set of write data from the write data register to a backup data register to preserve the first set of write data in event of a failure to successfully write the first set of write data to the bitcell array; the write logic copying the second set of write data from the cache register to the write data register after the first set of write data is transferred to the backup data register and preserving the second set of write data in the cache register; and data recovery logic of the memory controller determining whether the first set of write data was successfully written to the bitcell array, and in response to a determination that writing the first set of write data to the bitcell array failed, outputting the first set of write data preserved in the backup data register. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A system, comprising:
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a central processing unit; and a memory component, the memory component including a bitcell array and a memory controller configured to control memory read and memory write operations directed to the bitcell array, the memory controller including a cache register, a write data register, and a backup register, the memory controller further including; write logic configured to write a first set of write data to the bitcell array from the write data register, and to cache a second set of write data in a cache register; data preservation logic configured to transfer the first set of write data from the write data register to a backup data register to preserve the first set of write data in event of a failure to successfully write the first set of write data to the bitcell array wherein the write logic is further configured to copy the second set of write data from the cache register to the write data register after the first set of write data is transferred to the backup register, the data preservation logic being further configured to preserve the second set of write data in the cache register; and data recovery logic of the memory controller configured to determine whether the first set of write data was successfully written to the bitcell array, and in response to a determination that writing the first set of write data to the bitcell array failed, output the first set of write data preserved in the backup data register. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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Specification