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Data preservation and recovery in a memory component

  • US 10,268,578 B1
  • Filed: 09/29/2017
  • Issued: 04/23/2019
  • Est. Priority Date: 09/29/2017
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a memory component, the memory component including a bitcell array and a memory controller configured to control memory read and memory write operations directed to the bitcell array, the memory controller including a cache register, a write data register, and a backup register, the memory controller further including;

    write logic configured to write a first set of write data to the bitcell array from the write data register, and to cache a second set of write data in a cache register;

    data preservation logic configured to transfer the first set of write data from the write data register to a backup data register to preserve the first set of write data in event of a failure to successfully write the first set of write data to the bitcell array wherein the write logic is further configured to copy the second set of write data from the cache register to the write data register after the first set of write data is transferred to the backup register, the data preservation logic being further configured to preserve the second set of write data in the cache register; and

    data recovery logic of the memory controller configured to determine whether the first set of write data was successfully written to the bitcell array, and in response to a determination that writing the first set of write data to the bitcell array failed, output the first set of write data preserved in the backup data register.

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