Determining timeout values for computing systems

• US 10,268,615 B2
• Filed: 08/22/2017
• Issued: 04/23/2019
• Est. Priority Date: 08/22/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Baysah, Irving G., Cordero, Edgar R., Gollub, Marc A., Mulkey, Lucus W., Saetow, Anuwat
• Primary Examiner(s): Mamo, Elias
• Application Number:
  US15/683,347
• Publication Number:
  US 20190065421A1
• Time in Patent Office: 609 Days
• Field of Search: None
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G06F 2213/0002 Serial port, e.g. RS232C
• CPC Class Codes: G06F 2213/0026 PCI express

Abstract

A Local Timer Engine (LTE) is disclosed. For an initiator in a computing system, the LTE measures a respective time delay for each of a plurality of routes between the initiator and a plurality of destinations. For each of the plurality of routes, the LTE determines a respective timeout value based on the measured respective time delay for the route and determines a unique memory mapped address identifying the route. The initiator sends a request to the LTE for a timeout value. The LTE determines a proper timeout value and provides the proper timeout value to the initiator.

Claims

1. An integrated circuit, comprising:

an initiator configured to send commands to a plurality of destinations; and

a timer engine configured to;

for the initiator, measure a respective time delay for each of a plurality of routes between the initiator and the plurality of destinations, wherein the respective time delay indicates a time period from when the initiator sends a command to one of the plurality of destinations to when the initiator receives a corresponding response;

for each of the plurality of routes, determine a respective timeout value based on the measured respective time delay for the route;

for each of the plurality of routes, determine a unique memory mapped address identifying the route; and

wherein the initiator is further configured to;

upon determining to send a command to one of the plurality of destinations, send a request to the timer engine for a timeout value, wherein the request includes a memory address for an operation;

receive the requested timeout value from the timer engine; and

after sending the command to the destination, determine whether a response to the command is received within a time period indicated by the received timeout value.

2. The integrated circuit of claim 1, wherein at least one of the plurality of destinations is integrated on a different integrated circuit from the initiator.

3. The integrated circuit of claim 1, wherein at least one of the plurality of routes represents a group of routes that use a same timeout value.

4. The integrated circuit of claim 1, upon detecting data congestion on one of the plurality of routes, the timer engine is further configured to update the timeout value for the route.

5. The integrated circuit of claim 4, wherein the timer engine is further configured to update the timeout value for the route by applying a congestion coefficient to the timeout value for the route.

6. The integrated circuit of claim 1, upon detecting that a memory is moved to a new location and assigned to a new destination, the timer engine is further configured to update the timeout value for the route between the initiator and the new destination.

7. The integrated circuit of claim 6, wherein the timer engine is further configured to update the timeout value for the route by using idle cycles to measure the time delay between the initiator and the new destination.

8. A computing system, comprising:

an initiator configured to send commands;

a plurality of destinations configured to respond to the commands sent by the initiator;

wherein the initiator is coupled to the plurality of destinations through one or more buses; and

a timer engine configured to;

for the initiator, measure a respective time delay for each of a plurality of routes between the initiator and the plurality of destinations, wherein the respective time delay indicates a time period from when the initiator sends a command to one of the plurality of destinations to when the initiator receives a corresponding response;

for each of the plurality of routes, determine a respective timeout value based on the measured respective time delay for the route;

for each of the plurality of routes, determine a unique memory mapped address identifying the route; and

wherein the initiator is further configured to;

upon determining to send a command to one of the plurality of destinations, send a request to the timer engine for a timeout value, wherein the request includes a memory address for an operation;

receive the requested timeout value from the timer engine; and

after sending the command to the destination, determine whether a response to the command is received within a time period indicated by the received timeout value.

9. The computing system of claim 8, wherein at least one of the plurality of destinations is integrated on a different integrated circuit from the initiator.

10. The computing system of claim 8, wherein at least one of the plurality of routes represents a group of routes that use a same timeout value.

11. The computing system of claim 8, upon detecting data congestion on one of the plurality of routes, the timer engine is further configured to update the timeout value for the route.

12. The computing system of claim 11, wherein the timer engine is further configured to update the timeout value for the route by applying a congestion coefficient to the timeout value for the route.

13. The computing system of claim 8, upon detecting that a memory is moved to a new location and assigned to a new destination, the timer engine is further configured to update the timeout value for the route between the initiator and the new destination.

14. The computing system of claim 13, wherein the timer engine is further configured to update the timeout value for the route by using idle cycles to measure the time delay between the initiator and the new destination.

15. A method, comprising:

measuring, by a timer engine, a respective time delay for each of a plurality of routes between an initiator and a plurality of destinations, wherein the respective time delay indicates a time period from when the initiator sends a command to one of the plurality of destinations to when the initiator receives a corresponding response;

for each of the plurality of routes, determining a respective timeout value based on the measured respective time delay for the route;

for each of the plurality of routes, determining a unique memory mapped address identifying the route;

upon determining to send a command to one of the plurality of destinations, sending, by the initiator, a request to the timer engine for a timeout value, wherein the request includes a memory address for an operation;

receiving the requested timeout value from the timer engine; and

after sending the command to the destination, determining whether a response to the command is received within a time period indicated by the received timeout value.

16. The method of claim 15, wherein at least one of the plurality of routes represents a group of routes that use a same timeout value.

17. The method of claim 15, further comprising:

upon detecting data congestion on one of the plurality of routes, updating the timeout value for the route by the timer engine.

18. The method of claim 17, further comprising:

updating the timeout value for the route by applying a congestion coefficient to the timeout value for the route.

19. The method of claim 15, further comprising:

upon detecting that a memory is moved to a new location and assigned to a new destination, updating the timeout value for the route between the initiator and the new destination by the timer engine.

20. The method of claim 19, further comprising:

updating the timeout value for the route by using idle cycles to measure the time delay between the initiator and the new destination.