Apparatus for connecting non-volatile memory locally to a GPU through a local switch

• US 10,268,620 B2
• Filed: 12/23/2016
• Issued: 04/23/2019
• Est. Priority Date: 12/23/2016
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Osqueizadeh, Nima
• Primary Examiner(s): Martinez, David E
• Application Number:
  US15/389,747
• Publication Number:
  US 20180181518A1
• Time in Patent Office: 851 Days
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

Described herein are apparatus for connecting a first memory architecture locally to a graphics processing unit (GPU) through a local switch, where the first memory architecture can be a non-volatile memory (NVM) or other similarly used memories, for example, along with associated controllers. The apparatus includes the GPU(s) or discrete GPU(s) (dGPU(s)) (collectively GPU(s)), second memory architectures associated with the GPU(s), the local switch, first memory architecture(s), first memory architecture controllers or first memory architecture connector(s). In an implementation, the local switch is part of the GPU. The apparatus can also include a controller for distributing a large transaction among multiple first memory architectures. In an implementation, the first memory architectures can be directly connected to the GPU. In an implementation, the apparatus is user configurable. In an implementation, the apparatus is a solid state graphics (SSG) card.

Claims

1. A solid state graphics (SSG) card, comprising:

a plurality of first memory architecture units;

at least one graphics processing unit (GPU);

a second memory architecture associated with each GPU;

a local switch coupled to each of the first memory architecture units and the at least one GPU; and

a redundant array of independent drives (RAID) assist unit connected to each of the plurality of first memory architecture units and the local switch, the RAID assist unit segmenting and distributing a data transaction amongst the plurality of first memory architecture units,

wherein the first memory architecture units and the local switch directly process data transactions between a second memory architecture and the first memory architecture units in response to a data transfer command.

2. The SSG card of claim 1, wherein each first memory architecture unit is powered by an in-card power supply.

3. The SSG card of claim 1, wherein each first memory architecture unit includes a first memory architecture and an associated first memory architecture controller.

4. The SSG card of claim 1, wherein each first memory architecture unit includes a first memory architecture connector on the SSG card and a first memory architecture drive for connecting to the first memory architecture connector, wherein each first memory architecture drive includes a first memory architecture and an associated first memory architecture controller.

5. The SSG card of claim 4, wherein each first memory architecture drive is powered by an off-card power supply.

6. The SSG card of claim 1, wherein each first memory architecture unit includes a ball grid array (BGA) mount on the SSG card and a first memory architecture drive for connecting to the BGA mount, wherein each first memory architecture drive includes a first memory architecture and an associated first memory architecture controller.

7. The SSG card of claim 6, wherein each BGA mount is powered by an in-card power supply.

8. The SSG card of claim 1, wherein the local switch is integrated with one of the at least one GPU.

9. The SSG card of claim 1, wherein the first memory architecture unit is a non-volatile memory (NVM) unit and the second memory architecture is local memory.

10. A solid state graphics (SSG) card, comprising:

graphics processing unit (GPU) having at least one integrated first memory architecture controller and an integrated local switch;

the GPU having an associated second memory architecture; and

at least one first memory architecture unit connected to the at least one first memory architecture controller,

wherein the integrated local switch of the GPU directly processes data transactions between a second memory architecture and the at least one first memory architecture in response to a data transfer command.

11. The SSG card of claim 10, wherein each first memory architecture unit is powered by an in-card power supply.

12. The SSG card of claim 10, wherein each first memory architecture unit includes a first memory architecture connector on the SSG card and a first memory architecture drive for connecting to the first memory architecture connector, wherein each first memory architecture drive includes a first memory architecture.

13. The SSG card of claim 12, wherein each first memory architecture drive is powered by an off-card power supply.

14. The SSG card of claim 10, wherein each first memory architecture unit includes a ball grid array (BGA) mount on the SSG card and a first memory architecture drive for connecting to the BGA mount, wherein each first memory architecture drive includes a first memory architecture.

15. The SSG card of claim 14, wherein each BGA mount is powered by an in-card power supply.

16. The SSG card of claim 14, wherein the first memory architecture controller is a non-volatile memory (NVM) controller, the at least one first memory architecture unit is a NVM unit and the second memory architecture is local memory.