Memory package, memory module including the same, and operation method of memory package

• US 10,269,394 B2
• Filed: 11/22/2017
• Issued: 04/23/2019
• Est. Priority Date: 02/01/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Chankyung, Kang, Uksong, Kim, Nam Sung
• Primary Examiner(s): Sadler, Nathan
• Application Number:
  US15/820,473
• Publication Number:
  US 20180108383A1
• Time in Patent Office: 517 Days
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 14/0009 in which the volatile element is a DRAM cell
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.

Claims

1. A memory package comprising:

a nonvolatile memory chip;

a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip; and

a logic chip including a data managing unit, the data managing unit configured to;

receive data from an external device external to the memory package;

determine an attribute of the received data; and

write the received data into one of the volatile memory chip

and the nonvolatile memory chip based on the determined attribute,

wherein the volatile memory chip, the nonvolatile memory chip and the logic chip are vertically stacked and connected to each other through a through silicon via,

wherein the attribute indicates whether the received data are hot data or cold data, the hot data being data frequently accessed by the external device and the cold data being data not frequently accessed by the external device respectively,

the data managing unit is configured to set a first address for the hot data to be written into the volatile memory chip, and to set a second address for the cold data to be written into the nonvolatile memory chip,

the logic chip is configured to receive a refresh command from the external device, and perform a refresh operation on the volatile memory chip in response to the refresh command,

the data managing unit is further configured to determine a first data stored in the nonvolatile memory chip as hot data and migrate the first data to the volatile memory chip through a migration operation, and

both of the refresh operation and the migration operation occur in response to the refresh command.

2. The memory package of claim 1, wherein the volatile memory chip is a dynamic random access memory (DRAM) device and the nonvolatile memory chip is a NAND flash memory device.

3. The memory package of claim 2, wherein the memory package communicates with the external device based on a double data rate (DDR) interface.

4. The memory package of claim 3, wherein the NAND flash memory device comprises a three-dimensional (3D) memory array.

5. The memory package of claim 1, wherein the data managing unit is configured to determine whether the received data is hot data or cold data based on at least one of size of the received data, type of the received data, and header information included in the received data.

6. The memory package of claim 5, wherein the logic chip further includes a nonvolatile memory managing unit, and the nonvolatile memory managing unit is configured to perform a garbage collection operation and a wear leveling operation on the nonvolatile memory chip.

7. The memory package of claim 5, wherein the logic chip further includes an address managing unit, and the address managing unit is configured to manage addresses of the nonvolatile memory chip and the volatile memory chip.

8. The memory package of claim 7, wherein the address managing unit is configured to receive an address from an external device and convert the received address for accessing the volatile memory chip when data to be accessed are stored in the volatile memory chip, and to convert the received address for accessing the nonvolatile memory chip when data to be accessed are stored in the nonvolatile memory chip.

9. The memory package of claim 8, wherein the logic chip is further configured to transmit a waiting signal to the external device, and the waiting signal indicates whether the nonvolatile memory chip is ready to be accessed or not.

10. The memory package of claim 1, wherein the data managing unit is further configured to determine a first data stored in the nonvolatile memory chip as hot data and migrate the first data to the volatile memory chip through a migration operation.

11. The memory package of claim 10, wherein the migration operation is initiated by the logic chip and is performed through the through silicon via.

12. A memory package comprising:

a package substrate;

a plurality of nonvolatile memory chips disposed on the package substrate, the plurality of nonvolatile memory chips being vertically stacked in a stack of chips that includes only nonvolatile memory chips and connected each other by through-silicon vias;

a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip; and

a logic chip including a data managing unit, the data managing unit configured to;

receive data from an external device external to the memory package;

determine an attribute of the received data; and

write the received data into one of the volatile memory chip and the nonvolatile memory chip based on the determined attribute,

wherein the volatile memory chip and the logic chip are vertically stacked, and disposed on the package substrate horizontally spaced apart from the plurality of nonvolatile memory chips,

wherein the attribute indicates whether the received data are hot data or cold data, the hot data being data frequently accessed by the external device and the cold data being data not frequently accessed by the external device respectively,

the data managing unit is configured to set a first address for the hot data to be written into the volatile memory chip, and to set a second address for the cold data to be written into the nonvolatile memory chip,

the logic chip is configured to receive a refresh command from the external device, and perform a refresh operation on the volatile memory chip in response to the refresh command,

the data managing unit is further configured to determine a first data stored in the nonvolatile memory chip as hot data and migrate the first data to the volatile memory chip through a migration operation, and

both of the refresh operation and the migration operation occur in response to the refresh command.

13. The memory package of claim 12, wherein the plurality of nonvolatile memory chips and the logic chip are connected through a migration channel which comprises a conductive signal bus included in the package substrate.

14. The memory package of claim 13, wherein the migration operation is initiated by the logic chip and is performed through the migration channel.

15. The memory package of claim 12, wherein the volatile memory chip is a dynamic random access memory (DRAM) device and the nonvolatile memory chip is a NAND flash memory device.

16. The memory package of claim 15, wherein the memory package communicates with the external device based on a double data rate (DDR) interface.

17. The memory package of claim 16, wherein the NAND flash memory device comprises a three-dimensional (3D) memory array.

19. The memory package of claim 12, wherein the logic chip further includes an address managing unit, and the address managing unit is configured to manage addresses of the nonvolatile memory chip and the volatile memory chip.

20. The memory package of claim 19, wherein the address managing unit is configured to receive an address from an external device and convert the received address for accessing the volatile memory chip when data to be accessed are stored in the volatile memory chip, and to convert the received address for accessing the nonvolatile memory chip when data to be accessed are stored in the nonvolatile memory chip.

21. The memory package of claim 13, wherein the data managing unit is configured to determine whether the received data is hot data or cold data based on at least one of size of the received data, type of the received data, and header information included in the received data.

18. The memory package of 12, wherein the logic chip further includes a nonvolatile memory managing unit, and the nonvolatile memory managing unit is configured to perform a garbage collection operation and a wear leveling operation on the nonvolatile memory chip.