Programmable inductor

• US 10,269,489 B2
• Filed: 03/15/2013
• Issued: 04/23/2019
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Lii, Mirng-Ji, Tsai, Hao-Yi, Chen, Hsien-Wei, Kuo, Hung-Yi, Wu, Nien-Fang
• Primary Examiner(s): Talpalatski, Alexander
• Assistant Examiner(s): Baisa, Joselito
• Application Number:
  US13/832,964
• Publication Number:
  US 20140266542A1
• Time in Patent Office: 2,230 Days
• Field of Search: 336137, 336142, 336144, 336146, 336147, 336150, 336200, 257415, 257531, 257529, 257528, 29623, 29605, 296021, 438132
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0046 with a conductive path having a bridge
• CPC Class Codes: H01F 41/042 by thin film techniques
• CPC Class Codes: H01F 41/045 Trimming
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor

Abstract

A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects.

Claims

1. An inductor comprising:

a first turn of conductive material in the inductor;

a second turn of conductive material in the inductor;

a third turn of conductive material in the inductor;

a first programmable interconnect connecting the first turn to the second turn, wherein the first programmable interconnect is located fully above a semiconductor substrate and wherein the first programmable interconnect comprises a fuse physically located between a semiconductor substrate and a conductive portion of the inductor, the fuse having a first longitudinal axis;

a second programmable interconnect connecting the third turn and the second turn, wherein the second programmable interconnect comprises a second fuse with a second longitudinal axis, the second longitudinal axis intersecting the first longitudinal axis at an acute angle in a top down view;

an active device at least partially located over and within the semiconductor substrate; and

an interlayer dielectric located between the first programmable interconnect and the semiconductor substrate in a direction perpendicular to a major surface of the semiconductor substrate, wherein the interlayer dielectric comprises a first material throughout the interlayer dielectric.

2. The inductor of claim 1, wherein the first programmable interconnect is connected to the second turn through a first via and wherein the second programmable interconnect is connected to the second turn through a second via, the second via having a different dimension than the first via.

3. The inductor of claim 1, wherein the first programmable interconnect has a first dimension and the second programmable interconnect has a second dimension different from the first dimension.

4. The inductor of claim 3, wherein the second programmable interconnect has an hourglass shape with a neck.

5. The inductor of claim 4, wherein the first programmable interconnect has a rectangular shape.

6. The inductor of claim 1, wherein the first programmable interconnect is connected to the second turn through a first groups of vias and wherein the second programmable interconnect is connected to the second turn through a second group of vias, the second group of vias having a different number of vias than the first group of vias.

7. An inductor comprising:

a first interconnect connected to a first turn of conductive material through a first via and connected to a second turn of conductive material through a second via, wherein the first interconnect, the first via, and the second via form a first fuse with a first resistance, the first interconnect having a first longitudinal axis;

a second interconnect connected to the second turn of conductive material through a third via and connected to a third turn of conductive material through a fourth via, wherein the second interconnect, the third via, and the fourth via form a second fuse with a second resistance greater than the first resistance, the second interconnect having a second longitudinal axis; and

a third interconnect connected to the third turn through a fifth via and connected to the second turn through a sixth via, wherein the third interconnect, the fifth via, and the sixth via form a third fuse with a third resistance greater than the second resistance, wherein the first interconnect is located directly between a semiconductor substrate and either a portion of the first turn, a portion of the second turn, or a portion of the third turn in a direction perpendicular with a major surface of a semiconductor substrate, the third interconnect having a third longitudinal axis, wherein the second longitudinal axis is parallel with the first longitudinal axis and intersects the third longitudinal axis at an acute angle in a top down view.

8. The programmable inductor of claim 7, wherein the first via has a larger dimension than the third via and wherein the third via has a larger dimension than the fifth via.

9. The programmable inductor of claim 7, wherein the first via is part of a first group of vias connecting the first interconnect to the first turn of conductive material and wherein the third via is part of a second group of vias connecting the second interconnect to the second turn of conductive material, the first group of vias having a larger number of vias than the second group of vias.

10. The programmable inductor of claim 7, wherein the first interconnect has a first shape and the second interconnect has a second shape different from the first shape.

11. The programmable inductor of claim 10, wherein the first shape is a rectangle and the second shape is an hourglass shape.

12. The programmable inductor of claim 11, wherein the third interconnect has the second shape with different dimensions.

13. A method of manufacturing an inductor, the method comprising:

forming a first fuse over a substrate, wherein the first fuse comprises a first interconnect and a first via;

forming a second fuse over the substrate, wherein the second fuse comprises a second interconnect, a second via, and a third via, wherein the second fuse has a higher resistance than the first fuse, wherein the first fuse has a longitudinal axis which intersects the second fuse and the second fuse has a longitudinal axis which does not intersect the first fuse;

forming a first turn of conductive material in connection with the first via and the second via; and

forming a second turn of conductive material different from the first turn of conductive material in connection with the third via, wherein the first interconnect passes fully beneath either the first turn of conductive material or the second turn of conductive material such that either the first turn of conductive material or the second turn of conductive material are located directly above the first interconnect.

14. The method of claim 13, further comprising programming the inductor.

15. The method of claim 14, wherein the programming the inductor comprises applying a voltage to the first fuse and the second fuse such that the second fuse blows before the first fuse.

16. The method of claim 15, further comprising continuing the programming the inductor until the first fuse has blown.

17. The method of claim 13, wherein the first interconnect has a first shape and the second interconnect has the first shape with a smaller dimension than the first interconnect.

18. The method of claim 13, wherein the first via has a first dimension and wherein the second via has a second dimension different from the first dimension.

19. The method of claim 13, wherein the first via is part of a first group of vias physically connected to the first interconnect and wherein the second via is part of a second group of vias physically interconnect to the second interconnect, the first group of vias having a different number of vias than the second group of vias.

20. The method of claim 13, wherein the first programmable interconnect is located directly between a semiconductor substrate and the first turn.