High resistivity silicon-on-insulator substrate comprising an isolation region

• US 10,269,617 B2
• Filed: 06/15/2017
• Issued: 04/23/2019
• Est. Priority Date: 06/22/2016
• Status: Active Grant

• Current Assignee: GlobalWafers Co., Ltd. (Sino-American Silicon Products Incorporated)
• Original Assignee: GlobalWafers Co., Ltd. (Sino-American Silicon Products Incorporated)
• Inventors: Peidous, Igor, Libbert, Jeffrey L.
• Primary Examiner(s): Rodela, Eduardo A
• Assistant Examiner(s): Rahim, Nilufa
• Application Number:
  US15/623,519
• Publication Number:
  US 20170372946A1
• Time in Patent Office: 677 Days
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02634 Homoepitaxy
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/3226 of silicon on insulator
• CPC Class Codes: H01L 21/761 : PN junctions
• CPC Class Codes: H01L 21/76254 : with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 29/0646 : PN junctions
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

Claims

1. A method of preparing a multilayer structure, the method comprising:

implanting arsenic, As⁺, ions at a dosage between about 1×

10¹² atoms/cm² and about 5×

10¹⁴ atoms/cm² at an implant energy between about 10 kev and 50 keV through a front surface of a single crystal semiconductor handle substrate to thereby form an isolation region comprising arsenic-doped semiconductor, wherein the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge of the single crystal semiconductor handle substrate joining the front and back surfaces of the single crystal semiconductor handle substrate, a central plane of the single crystal semiconductor handle substrate between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a bulk resistivity of at least about 500 ohm-cm and further wherein the arsenic, As⁺, ions are implanted to a depth of between about 20 angstroms and about 400 angstroms as measured from the front surface of the single crystal semiconductor handle substrate toward the central plane of the single crystal semiconductor handle substrate;

depositing a dielectric layer on the front surface of the single crystal semiconductor handle substrate; and

bonding a front surface of a single crystal semiconductor donor substrate to the dielectric layer of the single crystal semiconductor handle substrate to thereby form a bonded multilayer structure comprising the single crystal semiconductor handle substrate, the isolation region, the dielectric layer, and the single crystal semiconductor donor substrate, wherein the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor donor substrate and the other of which is a back surface of the single crystal semiconductor donor substrate, a circumferential edge of the single crystal semiconductor donor substrate joining the front and back surfaces of the single crystal semiconductor donor substrate, and a central plane of the single crystal semiconductor donor substrate between the front and back surfaces of the single crystal semiconductor donor substrate, and further wherein the single crystal semiconductor donor substrate comprises a cleave plane.

2. The method of claim 1 wherein the single crystal semiconductor handle substrate comprises silicon, and the isolation region comprising arsenic-doped silicon.

3. The method of claim 1 wherein the single crystal semiconductor handle substrate comprises a silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

4. The method of claim 1 wherein the bulk resistivity of the single crystal semiconductor handle substrate is between about 500 Ohm-cm and about 100,000 Ohm-cm.

5. The method of claim 1 wherein the bulk resistivity of the single crystal semiconductor handle substrate is between about 2000 Ohm-cm and about 10,000 Ohm-cm.

6. The method of claim 1 wherein the bulk resistivity of the single crystal semiconductor handle substrate is between about 3000 Ohm-cm and about 10,000 Ohm-cm.

7. The method of claim 1 wherein the bulk resistivity of the single crystal semiconductor handle substrate is between about 3000 Ohm-cm and about 5,000 Ohm-cm.

8. The method of claim 1 wherein the arsenic, As⁺, ions are implanted to a depth of between about 50 angstroms and about 200 angstroms as measured from the front surface of the single crystal semiconductor handle substrate toward the central plane of the single crystal semiconductor handle substrate.

9. The method of claim 1 wherein the isolation region has a thickness between about 200 angstroms and about 10,000 angstroms.

10. The method of claim 1 wherein the dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and a combination thereof.

11. The method of claim 1 wherein the dielectric layer has a thickness of at least about 10 nanometer.

12. The method of claim 1 wherein the front surface of the single crystal semiconductor donor substrate comprises a semiconductor oxide layer.

13. The method of claim 1 further comprising mechanically cleaving the bonded structure at the cleave plane of the single crystal semiconductor donor substrate to thereby prepare a cleaved multilayer structure comprising the single crystal semiconductor handle substrate, the isolation region comprising arsenic-doped semiconductor, the dielectric layer, and a single crystal semiconductor device layer.

14. The method of claim 13 further comprising heating the cleaved multilayer structure at a temperature between about 1000°

C. and about 1200°

C. and for a duration between about 0.5 hours and about 8 hours to strengthen the bond between the single crystal semiconductor device layer and the single crystal semiconductor handle substrate.

15. The method of claim 1 further comprising oxidizing the front surface of the single crystal semiconductor handle substrate to form an oxidation layer at least about 1 nanometer thick before implanting the arsenic, As⁺, ions.

16. The method of claim 1 wherein the isolation region has a resistivity between about 0.25×

10⁶ Ohm-cm and about 1×

10¹⁴ ohm-cm.

17. The method of claim 1 wherein the isolation region has a resistivity between about 1×

10¹² Ohm-cm and about 1×

10¹⁴ ohm-cm.