Power overlay structure and method of making same

• US 10,269,688 B2
• Filed: 05/20/2013
• Issued: 04/23/2019
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Gowda, Arun Virupaksha, McConnelee, Paul Alan, Chauhan, Shakti Singh
• Primary Examiner(s): Muse, Ismail A
• Assistant Examiner(s): Reddington, Patricia D
• Application Number:
  US13/897,685
• Publication Number:
  US 20140264800A1
• Time in Patent Office: 2,164 Days
• Field of Search: 257713
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/9222 Sequential connecting processes
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49568 specifically adapted to facilitate heat dissipation
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

Claims

1. A semiconductor device package comprising:

a dielectric layer;

an adhesive layer applied to a surface of the dielectric layer;

a semiconductor device having a first surface coupled to the dielectric layer by way of the adhesive layer, the first surface having at least one contact pad positioned thereon;

a conducting shim having a first surface coupled to the dielectric layer by way of the adhesive layer;

an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim; and

a metallization layer coupled to the first surface of the semiconductor device and the first surface of the conducting shim, the metallization layer extending through the dielectric layer to contact the at least one contact pad of the semiconductor device and electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

2. The semiconductor device package of claim 1 wherein the semiconductor device comprises a power device.

3. The semiconductor device package of claim 1 wherein the second surface of the semiconductor device and the second surface of the conducting shim are substantially co-planar.

4. The semiconductor device package of claim 1 further comprising a thermal interface layer coating a second surface of the heatspreader, the thermal interface layer comprising a material that is electrically insulating and thermally conductive.

5. The semiconductor device package of claim 4 wherein the thermal interface layer comprises at least one of an organic material and a plurality of electrically conducting particles suspended in a resin.

6. The semiconductor device package of claim 4 further comprising a heat sink coupled to the thermal interface layer.

7. The semiconductor device package of claim 1 further comprising a conductive contact layer coupling the semiconductor device and the conducting shim to the heatspreader.

8. The semiconductor device package of claim 1 wherein a second surface of the heatspreader is exposed to ambient air for convective heat transfer.

9. The semiconductor device package of claim 1 further comprising an encapsulant surrounding the semiconductor device and the conducting shim.

21. The semiconductor package of claim 1 wherein the first surface of the semiconductor device and the first surface of the conducting shim are substantially co-planar.

10. A method of forming a semiconductor device package comprising:

providing a dielectric layer;

applying an adhesive layer to a surface of the dielectric layer;

coupling a first surface of a semiconductor device to the dielectric layer by way of the adhesive layer;

coupling a first surface of a conductive shim to the dielectric layer by way of the adhesive layer;

disposing a heatspreader on a second surface of the semiconductor device and a second surface of the conductive shim, the heatspreader electrically coupling the semiconductor device to the conductive shim; and

forming a metal interconnect structure on a surface of the dielectric layer, the metal interconnect structure extending through vias formed in the dielectric layer to contact the first surface of the semiconductor device and the first surface of the conductive shim.

11. The method of claim 10 further comprising encapsulating the semiconductor device, the conductive shim, and at least a portion of the heatspreader with a polymeric material.

12. The method of claim 10 further comprising forming a thermal interface layer on a top surface of the heatspreader.

13. The method of claim 12 further comprising coupling a heat sink to the thermal interface layer.

14. The method of claim 12 further comprising underfilling a space between the dielectric layer and the thermal interface layer with a dielectric material.

15. A power overlay (POL) structure comprising:

an insulating substrate;

a power device attached to the insulating substrate via an adhesive layer;

an electrically conducting shim attached to the insulating substrate via the adhesive layer, the electrically conducting shim positioned adjacent the power device on the insulating substrate;

an electrically and thermally conducting slab coupled to a top surface of the power device and a top surface of the conducting shim; and

a metallization layer extending through the insulating substrate, the metallization layer electrically coupled to contact locations on a first surface and a second surface of the power device.

16. The POL structure of claim 15 wherein the top surfaces of the power device and the conducting shim are substantially co-planar.

17. The POL structure of claim 15 further comprising an electrically insulating layer having a first side coupled to the electrically conducting shim.

18. The POL structure of claim 17 wherein the electrically insulating layer comprises an organic, thermally conductive material.

19. The POL structure of claim 18 further comprising a heat sink coupled to a second side of the electrically insulating layer.

20. The POL structure of claim 19 wherein the electrically insulating layer comprises a multi-layer substrate, the multi-layer substrate comprising:

a first layer having a first surface coupled to the electrically conducting heat spreader;

a second layer having a first surface coupled to the heat sink; and

a ceramic layer coupled between the first and second layers.