Semiconductor structure with ultra thick metal and manufacturing method thereof

• US 10,269,701 B2
• Filed: 10/02/2015
• Issued: 04/23/2019
• Est. Priority Date: 10/02/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lu, Chen-Fa, Tsai, Cheng-Yuan, Hsu, Ching-Chung, Chang, Chung-Long
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US14/874,147
• Publication Number:
  US 20170098606A1
• Time in Patent Office: 1,299 Days
• Field of Search: 257531
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers

Abstract

The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.

Claims

1. A semiconductor structure, comprising:

a substrate;

a metal layer over the substrate;

an ultra thick metal (UTM) over the metal layer, the UTM comprising a top surface;

a photo-sensitive polymer layer surrounding the UTM, the top surface of the UTM being coplanar with a top surface of the photo-sensitive polymer layer; and

a post passivation interconnect (PPI) over the UTM, the PPI comprising a vertical sidewall,

wherein a thickness of the UTM is equal to or greater than 6 micrometer, the UTM and the metal layer being composed of substantial identical material.

2. The semiconductor structure of claim 1, wherein UTM is positioned in a trapezoidal trench having a shorter side in proximity to the metal layer the, an acute angle between a sidewall and an extension of the shorter side of the trapezoidal trench is in a range of from about 40 degrees to about 70 degrees.

3. The semiconductor structure of claim 1, further comprising an isolation layer between the metal layer and the UTM.

4. The semiconductor structure of claim 3, further comprising a via in a passivation layer above the UTM, electrically connecting the PPI and the UTM.

5. The semiconductor structure of claim 1, wherein a critical dimension of a line pitch of the UTM is in a range of from about 20 μ

m to about 375 μ

m.

6. The semiconductor structure of claim 1, further comprising a barrier layer between the UTM and a dielectric layer surrounding the UTM.

7. The semiconductor structure of claim 6, wherein the barrier layer comprises SiON.

8. A semiconductor structure, comprising:

a substrate;

a metal layer over the substrate;

an inductor over the metal layer, comprising;

a lower metal having a top surface;

a photo-sensitive polymer layer surrounding the lower metal, the top surface of the lower metal being coplanar with a top surface of the photo-sensitive polymer layer; and

an upper metal electrically connecting to the lower metal through a via; and

an isolation layer between the metal layer and the lower metal of the inductor,

wherein a thickness of the lower metal is equal to or greater than 6 μ

m.

9. The semiconductor structure of claim 8, further comprising a magnetic core between the upper metal and the lower metal.

10. The semiconductor structure of claim 9, wherein the via and the magnetic core are in a passivation layer below the upper metal.

11. The semiconductor structure of claim 8, wherein the upper metal is a post passivation interconnect (PPI) having a thickness equal to or greater than about 10 μ

m.

12. The semiconductor structure of claim 8, wherein the lower metal comprises a line pattern, a cross section of the line pattern comprising an upper surface in proximity to the via and a lower surface opposite to the upper surface,

wherein a length of the upper surface is greater than a length of the lower surface, and

a ratio of one half of a length difference between the upper surface and the lower surface and the thickness of the lower metal is in a range of from about 0.8 to about 2.8.

13. The semiconductor structure of claim 8, wherein the lower metal comprises a substantially parallel line pattern having a critical dimension of a line pitch of form about 20 μ

m to about 375 μ

m.

14. A method for manufacturing a semiconductor structure, comprising:

patterning a photo-sensitive polymer layer with a plurality of trenches by a first mask, the first mask having a first line pitch;

curing the photo-sensitive polymer layer after patterning the same with a plurality of trenches;

patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, the second mask having a second line pitch, the first mask and the second mask having substantially identical pattern, and the second line pitch being greater than the first line pitch; and

selectively plating conductive material in the plurality of trenches while the photoresist being on the mesa.

15. The method of claim 14, wherein the patterning the photo-sensitive polymer layer with a plurality of trenches comprises forming the plurality of trenches having a depth equal to or greater than 6 μ

m.

16. The method of claim 14, further comprising:

removing the photoresist after the selectively plating so as to expose a sidewall of the as-plated conductive material on the mesa; and

planarizing the conductive material to be coplanar with the mesa.

17. The method of claim 14, further comprising:

forming a seed layer for the conductive materials conformal to the plurality of trenches before the patterning the photoresist.