Semiconductor structure and manufacturing method thereof

• US 10,269,795 B2
• Filed: 10/23/2017
• Issued: 04/23/2019
• Est. Priority Date: 12/18/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
• Primary Examiner(s): Kielin, Erik
• Application Number:
  US15/790,129
• Publication Number:
  US 20180061831A1
• Time in Patent Office: 547 Days
• Field of Search: None
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer.

Claims

1. A method for manufacturing a semiconductor structure, the method comprising:

forming a dielectric layer on a source/drain structure adjacent to a first spacer of a gate structure, wherein a second spacer is disposed diametrically opposite the gate structure relative to the first spacer;

removing an upper portion of the dielectric layer, such that the dielectric layer and the first spacer of the gate structure form a recess;

rounding a top portion of the first spacer adjacent to the recess to have a rounded top corner and rounding a top portion of the second spacer to have a rounded top corner having a radius of curvature that is different than a radius of curvature of the rounded top corner of the top portion of the first spacer;

forming a protection layer at least on the rounded top corner of the top portion of the first spacer; and

forming a conductive via at least through the dielectric layer to be electrically connected to the source/drain structure.

2. The method of claim 1, further comprising:

forming a contact etch stop layer at least on a sidewall of the top portion of the first spacer before the forming the dielectric layer.

3. The method of claim 2, wherein the forming a contact etch stop layer comprises forming a portion of the contact etch stop layer on the source/drain structure.

4. The method of claim 2, wherein the rounding a top portion of the first spacer removes at least a portion of the contact etch stop layer from the sidewall of the top portion of the first spacer.

5. The method of claim 2, wherein the contact etch stop layer and the protection layer are made of different materials.

6. The method of claim 1, wherein the forming a protection layer comprises forming a portion of the protection layer on the dielectric layer.

7. The method of claim 6, wherein the forming a conductive via comprises:

forming a hole at least through the portion of the protection layer on the dielectric layer and the dielectric layer to expose a portion of the source/drain structure; and

forming a conductor in the hole and electrically connected to the exposed portion of the source/drain structure.

8. A method, comprising:

forming a contact etch stop layer in a recess between a first spacer of a first gate structure and a first spacer of a second gate structure;

forming a dielectric layer in the recess over the contact etch stop layer to conceal a sidewall of the contact etch stop layer; and

recessing the dielectric layer to expose a portion of the sidewall of the contact etch stop layer; and

etching the contact etch stop layer, the first spacer of the first gate structure, and a second spacer of the first gate structure diametrically opposite the first spacer of the first gate structure, wherein;

a top corner of the second spacer of the first gate structure is etched differently than a top corner of the first spacer of the first gate structure, and

the top corner of the second spacer of the first gate structure has a radius of curvature that is different than a radius of curvature of the top corner of the first spacer of the first gate structure.

9. The method of claim 8, wherein the etching the contact etch stop layer comprises etching the exposed portion of the sidewall of the contact etch stop layer.

10. The method of claim 8, further comprising:

forming a protection layer at least on the top corner of the first spacer of the first gate structure after the etching.

11. The method of claim 10, further comprising:

etching the protection layer and the contact etch stop layer to form a hole and expose a portion of a source/drain structure underlying the recess; and

forming a conductor in the hole and electrically connected to the exposed portion of the source/drain structure.

12. The method of claim 8, further comprising:

etching the contact etch stop layer a second time to form a hole and expose a portion of a source/drain structure underlying the recess; and

forming a conductor in the hole and electrically connected to the exposed portion of the source/drain structure.

13. A method, comprising:

forming a contact etch stop layer in a recess between a first spacer of a first gate structure and a first spacer of a second gate structure;

etching the contact etch stop layer, the first spacer of the first gate structure, and a second spacer of the first gate structure diametrically opposite the first spacer of the first gate structure, wherein;

a top corner of the second spacer of the first gate structure is etched differently than a top corner of the first spacer of the first gate structure, and

the top corner of the second spacer of the first gate structure has a radius of curvature that is different than a radius of curvature of the top corner of the first spacer of the first gate structure; and

forming a protection layer at least on the top corner of the first spacer of the first gate structure after the etching.

14. The method of claim 13, further comprising:

forming a dielectric layer in the recess over the contact etch stop layer, wherein the forming a protection layer comprises forming the protection layer over the dielectric layer.

15. The method of claim 14, wherein the forming a protection layer comprises forming the protection layer in contact with the contact etch stop layer.

16. The method of claim 14, comprising:

etching the protection layer, the dielectric layer, and the contact etch stop layer to form a hole and expose a portion of a source/drain structure; and

forming a conductor in the hole and electrically connected to the exposed portion of the source/drain structure.

17. The method of claim 13, wherein the forming a protection layer comprises forming the protection layer in contact with the contact etch stop layer.

18. The method of claim 13, further comprising:

etching the protection layer and the contact etch stop layer to form a hole and expose a portion of a source/drain structure; and

forming a conductor in the hole and electrically connected to the exposed portion of the source/drain structure.

19. The method of claim 13, wherein the contact etch stop layer and the protection layer are made of different materials.

20. The method of claim 13, wherein the contact etch stop layer and the protection layer are made of different materials.