Semiconductor device having a trench gate

• US 10,269,953 B2
• Filed: 12/27/2017
• Issued: 04/23/2019
• Est. Priority Date: 10/14/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Laforet, David, Ouvrard, Cedric
• Primary Examiner(s): Ahmed, Shahed
• Application Number:
  US15/855,256
• Publication Number:
  US 20180122934A1
• Time in Patent Office: 482 Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a gate structure extending from a first surface into a semiconductor portion and having a metal gate electrode and a gate dielectric separating the metal gate electrode from the semiconductor portion. An interlayer dielectric separates a first load electrode from the semiconductor portion, and includes a screen oxide layer thinner than the gate dielectric. A body zone and a source zone are formed in the semiconductor portion and directly adjoin the gate structure.

Claims

1. A semiconductor device, comprising:

a gate structure extending from a first surface into a semiconductor portion and comprising a metal gate electrode and a gate dielectric separating the metal gate electrode from the semiconductor portion;

an interlayer dielectric separating a first load electrode from the semiconductor portion, the interlayer dielectric comprising a screen oxide layer thinner than the gate dielectric; and

a body zone and a source zone formed in the semiconductor portion and directly adjoining the gate structure.

2. The semiconductor device of claim 1, wherein the interlayer dielectric further comprises at least one of a silicon oxide and a silicate glass.

3. The semiconductor device of claim 1, wherein the gate electrode includes a first portion extending from the first surface into the semiconductor portion and a second portion extending from the first surface through the screen oxide layer and into a further portion of the interlayer dielectric.

4. The semiconductor device of claim 1, further comprising:

field plate structures extending from the first surface into the semiconductor portion.

5. The semiconductor device of claim 4, wherein the gate structure forms a grid and the field plate structures are formed in meshes of the grid.

6. The semiconductor device of claim 4, wherein each field plate structure comprises an electrically conductive field electrode and a field dielectric that electrically insulates the field electrode from the semiconductor portion.

7. The semiconductor device of claim 6, wherein each field electrode is electrically connected to the source zone.

8. The semiconductor device of claim 1, wherein the gate structure includes a plurality of separated gate structure portions.

9. The semiconductor device of claim 1, wherein the gate dielectric is at least twice as thick as the screen oxide layer.

10. The semiconductor device of claim 1, wherein at least one of the source zone and the body zone directly adjoins the gate dielectric.

11. The semiconductor device of claim 1, wherein the screen oxide layer directly contacts the source zone at the first surface.

12. The semiconductor device of claim 11, wherein the screen oxide layer comprises an upper surface opposite from the first surface, and wherein the interlayer dielectric comprises an additional dielectric region disposed between the upper surface and the load electrode.

13. A semiconductor device, comprising:

a gate structure extending from a first surface into a semiconductor portion and comprising a metal gate electrode and a gate dielectric separating the gate electrode from the semiconductor portion;

an interlayer dielectric separating a first load electrode from the first surface, wherein the gate electrode includes a first portion extending from the first surface into the semiconductor portion and a second portion extending from the first surface into the interlayer dielectric; and

a body zone and a source zone formed in the semiconductor portion and directly adjoining the gate structure,

wherein the second portion of the gate electrode laterally covers and extends above the gate dielectric.

14. The semiconductor device of claim 13, wherein the interlayer dielectric comprises a screen oxide layer thinner than the gate dielectric.

15. The semiconductor device of claim 14, wherein the second portion of the gate electrode extends through the screen oxide layer and into the interlayer dielectric.

16. The semiconductor device of claim 14, wherein the gate dielectric is at least twice as thick as the screen oxide layer.

17. The semiconductor device of claim 13, wherein the interlayer dielectric comprises at least one of a silicon oxide and a silicate glass.

18. The semiconductor device of claim 13, further comprising:

field plate structures extending from the first surface into the semiconductor portion.

19. The semiconductor device of claim 18, wherein the gate structure forms a grid and the field plate structures are formed in meshes of the grid.

20. The semiconductor device of claim 18, wherein each field plate structure comprises an electrically conductive field electrode and a field dielectric that electrically insulates the field electrode from the semiconductor portion.

21. The semiconductor device of claim 20, wherein each field electrode is electrically connected to the source zone.

22. The semiconductor device of claim 13, wherein the gate structure includes a plurality of separated gate structure portions.