Envelope tracking current bias circuit with offset removal function and power amplifier

• US 10,270,395 B2
• Filed: 01/19/2018
• Issued: 04/23/2019
• Est. Priority Date: 07/18/2017
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Jo, Byeong Hak, Ha, Jong Ok, Kim, Jeong Hoon
• Primary Examiner(s): Tran, Khanh C
• Application Number:
  US15/875,463
• Publication Number:
  US 20190028060A1
• Time in Patent Office: 459 Days
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0233 by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
• CPC Class Codes: H03F 1/0266 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence

Abstract

An envelope tracking (ET) current bias circuit comprises an envelope detection circuit detecting an ET voltage from an input signal; a first voltage/current converting circuit converting a reference voltage into a direct current (DC) current and adjusting the DC current according to a first control signal; a second voltage/current converting circuit converting the ET voltage into an ET current, adjusting the ET current according to a second control signal, and removing a DC offset current from the ET current to provide an offset compensated ET current; and an arithmetic circuit calculating levels of the offset compensated ET current and the DC current to generate an ET bias current.

Claims

1. An envelope tracking (ET) current bias circuit, comprising:

an envelope detection circuit configured to detect an ET voltage from an input signal;

a first voltage/current converting circuit configured to convert a reference voltage into a direct current (DC) current and adjust the DC current according to a first control signal;

a second voltage/current converting circuit configured to convert the ET voltage into an ET current, adjust the ET current according to a second control signal, and remove a DC offset current from the ET current to provide an offset compensated ET current; and

an arithmetic circuit configured to calculate levels of the offset compensated ET current and the DC current to generate an ET bias current.

2. The ET current bias circuit of claim 1, wherein the second voltage/current converting circuit comprises a circuit structure configured the same as a circuit structure of the first voltage/current converting circuit to generate a DC offset compensation current corresponding to a DC offset current included in the ET current and remove the DC offset current by using the DC offset compensation current.

3. The ET current bias circuit of claim 1, wherein the second voltage/current converting circuit comprises:

a voltage/current converting circuit configured to provide the ET current adjusted according to the second control signal;

an offset current generating circuit configured to generate a DC offset compensation current corresponding to a DC offset current included in the ET current and provide the DC offset compensation current adjusted according to the second control signal; and

an offset removal circuit configured to remove the DC offset current included in the ET current by using the DC offset compensation current supplied from the offset current generating circuit.

4. The ET current bias circuit of claim 3, wherein the voltage/current converting circuit comprises:

a first current source circuit configured to comprise a first operational amplifier, a first resistance circuit, and a first metal oxide semiconductor (MOS) transistor circuit to generate a first current according to the ET voltage; and

a first current mirror circuit configured to comprise a second MOS transistor circuit connected to the first MOS transistor circuit by a current mirror to provide the ET current corresponding to the first current.

5. The ET current bias circuit of claim 4, wherein the offset current generating circuit comprises:

a second current source circuit configured to comprise a second operational amplifier, a second resistance circuit, and a third MOS transistor circuit to generate the DC offset compensation current according to the reference voltage;

a second current mirror circuit configured to comprise a fourth MOS transistor circuit connected to the third MOS transistor circuit by the current mirror to mirror the DC offset mirror current; and

a third current mirror circuit configured to be connected to the second current mirror circuit by the current mirror and remove the DC offset current from the ET current by using the DC offset compensation current.

6. The ET current bias circuit of claim 5, wherein the first resistance circuit is configured to adjust the ET current based on variations in a resistance value according to the second control signal, and the second resistance circuit is configured to adjust the DC offset compensation current based on variations in the resistance value according to the second control signal.

7. The ET current bias circuit of claim 1, wherein the envelope detection circuit comprises:

a rectifying circuit configured to detect the ET voltage from the input signal, wherein the ET voltage includes a DC offset voltage;

an offset voltage generating circuit configured to generating a DC offset compensation voltage corresponding to the DC offset voltage; and

an offset voltage cancellation circuit configured to subtract the DC offset compensation voltage from the DC offset voltage to provide the ET voltage from which the DC offset voltage is reduced.

8. The ET current bias circuit of claim 1, wherein the arithmetic circuit adds or subtracts the offset compensated ET current and the DC current to generate the ET bias current.

9. A power amplifier, comprising:

an envelope tracking (ET) current bias circuit configured to generate an ET bias current, based on an envelope of an input signal; and

a power amplification circuit configured to comprise a buffered bias circuit amplifying the ET bias current to provide a second ET bias current and a power amplifier receiving the second ET bias current to amplify the input signal,

wherein the ET current bias circuit comprises;

an envelope detection circuit configured to detect an ET voltage from the input signal;

a first voltage/current converting circuit configured to convert a reference voltage into a DC current and adjust the DC current according to a first control signal;

a second voltage/current converting circuit configured to convert the ET voltage into an ET current, adjust the ET current according to a second control signal, and remove a DC offset current from the ET current to provide an offset compensated ET current; and

an arithmetic circuit configured to calculate levels of the offset compensated ET current and the DC current to generate the ET bias current.

10. The power amplifier of claim 9, wherein the second voltage/current converting circuit comprises a circuit structure configured the same as a circuit structure of the first voltage/current converting circuit to generate a DC offset compensation current corresponding to the DC offset current included in the ET current and removes the DC offset current by using the DC offset compensation current.

11. The power amplifier of claim 9, wherein the second voltage/current converting circuit comprises:

a voltage/current converting circuit configured to provide the ET current adjusted according to the second control signal;

an offset current generating circuit configured to generate a DC offset compensation current corresponding to the DC offset current included in the ET current and provide the DC offset compensation current adjusted according to the second control signal; and

an offset removal circuit configured to remove the DC offset current included in the ET current by using the DC offset compensation current supplied from the offset current generating circuit.

12. The power amplifier of claim 11, wherein the voltage/current converting circuit comprises:

a first current source circuit configured to comprise a first operational amplifier, a first resistance circuit, and a first metal oxide semiconductor (MOS) transistor circuit to generate a first current according to the ET voltage; and

a first current mirror circuit configured to comprise a second MOS transistor circuit connected to the first MOS transistor circuit by a current mirror to provide the ET current corresponding to the first current.

13. The power amplifier of claim 12, wherein the offset current generating circuit comprises:

a second current source circuit configured to comprise a second operational amplifier, a second resistance circuit, and a third MOS transistor circuit to generate the DC offset compensation current according to the reference voltage;

a second current mirror circuit configured to comprise a fourth MOS transistor circuit connected to the third MOS transistor circuit by the current mirror to mirror the DC offset compensation current; and

a third current mirror circuit configured to be connected to the second current mirror circuit by the current mirror and remove the DC offset current from the ET current by using the DC offset compensation current.

14. The power amplifier of claim 13, wherein the first resistance circuit is configured to adjust the ET current based on variations in a resistance value according to the second control signal, and the second resistance circuit is configured to adjust the DC offset compensation current based on variations in the resistance value according to the second control signal.

15. The power amplifier of claim 9, wherein the envelope detection circuit comprises:

a rectifying circuit configured to detect the ET voltage from the input signal, wherein the ET voltage includes a DC offset voltage;

an offset voltage generating circuit configured to generate a DC offset compensation voltage corresponding to the DC offset voltage; and

an offset voltage cancellation circuit configured to subtract the DC offset compensation voltage from the DC offset voltage to provide the ET voltage from which the DC offset voltage is reduced.

16. The power amplifier of claim 9, wherein the power amplification circuit is further configured to receive an electric source voltage, wherein the electric source voltage is based on an envelope of the input signal or independent from the envelope of the input signal.

17. The power amplifier of claim 9, wherein the arithmetic circuit adds or subtracts the offset compensated ET current and the DC current based on one or more of a frequency band, a band width, a power mode, and a magnitude of output power of the power amplification circuit.