Demodulation of on-off-key modulated signals in signal isolator systems

• US 10,270,630 B2
• Filed: 09/15/2014
• Issued: 04/23/2019
• Est. Priority Date: 09/15/2014
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Yun, Ruida, Gaalaas, Eric C., Chen, Baoxing
• Primary Examiner(s): Tadese, Berhanu
• Application Number:
  US14/486,951
• Publication Number:
  US 20160080182A1
• Time in Patent Office: 1,681 Days
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits

Abstract

A receiver system for an on-off key (“OOK”) isolator system may include a receiver that generates an intermediate current signal based on an OOK input signal. The intermediate current may be provided at a first current level when the input signal has a first OOK state and a second current level when the input signal has a second OOK state. The system also may include an output driver to generate a voltage representation of the intermediate current signal. Performing signal processing in a current domain permits fast transitions between OOK states.

Claims

1. An on-off key (“

OOK”

) receiver system, comprising;

an isolator having a first side and a second side;

a receiver, coupled to the second side of the isolator, configured to, responsive to an OOK voltage input signal, generate a current signal based on the input signal, the current signal comprising a first current level when the input signal has a first OOK state and a second current level different than the first current level when the input signal has a second OOK state different than the first OOK state, and

an output driver configured to generate a voltage representation of the current signal.

2. The system of claim 1, wherein the receiver comprises:

a pair of first and second mismatched differential pair circuits having inputs for a differential input signal, each differential pair circuit comprising a pair of transistors one of which is smaller than the other,

a current mirror having a pair of current paths, a first current path coupled to the smaller transistors of the two differential pair circuits and a second current path coupled to an output terminal of the receiver, and

a plurality of current sources, a first current source coupled to the first differential pair circuit, a second current source coupled to the second differential pair circuit and a third current source coupled to the output terminal.

3. The system of claim 1, wherein the receiver comprises:

two pairs of mismatched differential pair circuits having inputs for a differential input signal, each differential pair circuit comprising a pair of transistors one of which is smaller than the other, wherein a device type of transistors in a first two of the differential pair circuits are complementary to a device type of transistors in the other two of the differential pair circuits,

a current mirror having a pair of current paths, a first current path coupled to the smaller transistors of the four differential pair circuits and a second current path coupled to an output terminal of the receiver,

current sources coupled to each of the differential pair circuits, and

an additional current source coupled to the output terminal.

4. The system of claim 1, wherein the output driver comprises an inverter.

5. The system of claim 1, wherein the output driver comprises:

an inverter and

means for applying positive feedback to an input of the output driver.

6. The system of claim 1, wherein the output driver comprises a plurality of inverters in cascade.

7. The system of claim 1, wherein the output driver comprises a current-limited inverter.

8. The system of claim 1, wherein the output driver comprises

an inverter, and

a filter coupled to an output of the inverter.

9. An on-off key (“

OOK”

) receiver system, comprising;

a pair of current sources,

a pair of current routers, each coupled to a respective current source of the pair of current sources, the current routers having a first conductivity pathway and a second conductivity pathway of lower conductivity than the first conductivity pathway, the first conductivity pathway of a first current router and the second conductivity pathway of a second current router having control inputs coupled to a first differential signal representing an OOK input signal and the first conductivity pathway of the second current router and the second conductivity pathway of the first current router having control inputs coupled to a second differential signal representing the OOK input signal,

a current output system to generate a current signal representing an aggregate amount of current passing through second conductivity pathways of the current routers; and

an output driver to generate a voltage representation of the current signal.

10. The system of claim 9, wherein the current routers comprise a differential pair of transistors having mismatched sizes.

11. The system of claim 9, wherein the output driver comprises an inverter.

12. The system of claim 9, wherein the output driver comprises:

an inverter and

means for applying positive feedback to an input of the output driver.

13. The system of claim 9, wherein the output driver comprises a plurality of inverters in cascade.

14. The system of claim 9, wherein the output driver comprises a current-limited inverter.

15. The system of claim 9, wherein the output driver comprises

an inverter, and

a filter coupled to an output of the inverter.

16. An on-off key (“

OOK”

) receiver system, comprising;

a pair of current mirrors, each having first and second legs, first legs of the two current mirrors coupled to an intermediate output node;

four differential pair circuits, each comprising a pair of mismatched transistors coupled to a respective current source, the transistors of the first two differential pair circuits having a different doping type than the transistors of the second two differential pair circuits, wherein

a larger transistor of each differential pair circuit is coupled to a second leg a first current mirror of the pair of current mirrors, and

a smaller transistor of each differential pair circuit is coupled to a second leg of a second current mirror of the pair of current mirrors; and

an output driver to generate an output voltage based on a current present at the intermediate output node.

17. The system of claim 16, wherein the output driver comprises an inverter.

18. The system of claim 16, wherein the output driver comprises:

an inverter, and

means for applying positive feedback to an input of the output driver.

19. The system of claim 16, wherein the output driver comprises a plurality of inverters in cascade.

20. The system of claim 16, wherein the output driver comprises a current-limited inverter.

21. The system of claim 16, wherein the output driver comprises

an inverter, and

a filter coupled to an output of the inverter.

22. A method of generating a digital voltage signal representing a differential on-off keyed input signal, comprising:

generating a current signal from an on-off key (OOK) signal received by an isolator device,

comparing the current signal to a reference current signal, and

generating a binary voltage signal having a value dependent on a result of the comparison of the current signal to the reference current signal.

23. The method of claim 22, wherein generating the current signal comprises using a plurality of voltage comparison circuits having complementary transistor types.

24. The method of claim 22, wherein generating the current signal comprises using a plurality of mismatched voltage comparison circuits to steer current based on whether the OOK signal is in an ON or OFF stage.

25. The method of claim 22, wherein the current signal is generated by:

routing a first instance of a predetermined amount of current between a first high permittivity current path and a first low permittivity current path in response to the input signal where, when the input signal is at a common mode level, a larger share of current passes through the first high permittivity current path than the first low permittivity current path but when the input signal is at a first limit, a larger share of the current passes through the first low permittivity current path than the first high permittivity current path,

routing a second instance of a predetermined amount of current between a second high permittivity current path and a second low permittivity current path in response to the input signal wherein, when the input signal is at a common mode level, a larger share of current passes through the second high permittivity current path than the second low permittivity current path but when the input signal is at a second limit, a larger share of the current passes through the second low permittivity current path than the second high permittivity current path, and

aggregating currents passed through the two low permittivity current paths.