Mechanism for creating friendly transactions with credentials
First Claim
1. A system for assigning tokens to transactions in a transactional memory execution environment, comprising:
- a memory;
a processor device; and
a system controller communicatively coupled to the processor device and the memory, wherein the system controller is configured to;
receive a first transaction having a first token of a first token type associated with the first transaction;
receive a request for a transaction potential conflict check between the first transaction and a second transaction, wherein the first transaction is using a cache line;
determine, in response to receiving the request for the transaction potential conflict check, whether the first transaction and the second transaction are conflicting, wherein determining whether the first transaction and the second transaction are conflicting includes at least determining whether the first transaction and the second transaction have a shared address space within the memory, the memory having one or more memory partitions supporting one or more address spaces;
in response to determining that the first transaction and the second transaction do not have the shared address space within the memory, assign the second transaction a second token of the first token type identical to the first token based on the transaction potential conflict check between the second transaction and the first transaction; and
suppress detection of cache coherent conflicts in response to assigning the second transaction the second token identical to the first token such that cache coherency protocols are ignored, wherein suppressing detection of the cache coherent conflicts allows the first transaction to write to the cache line and the second transaction to write to the cache line concurrently.
1 Assignment
0 Petitions
Accused Products
Abstract
One or more transactions may request or be assigned tokens within a transactional memory environment. A transaction may be created by at least one thread. A first transaction that includes a first token type may be received. A request may be received for a for a potential conflict check between the first transaction and a second transaction. In response to receiving the transaction potential conflict check, the first transaction and the second transaction are determined to be conflicting or not conflicting. The second transaction is assigned a token type in response to the determination of the transaction potential conflict check between the first transaction and the second transaction.
43 Citations
15 Claims
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1. A system for assigning tokens to transactions in a transactional memory execution environment, comprising:
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a memory; a processor device; and a system controller communicatively coupled to the processor device and the memory, wherein the system controller is configured to; receive a first transaction having a first token of a first token type associated with the first transaction; receive a request for a transaction potential conflict check between the first transaction and a second transaction, wherein the first transaction is using a cache line; determine, in response to receiving the request for the transaction potential conflict check, whether the first transaction and the second transaction are conflicting, wherein determining whether the first transaction and the second transaction are conflicting includes at least determining whether the first transaction and the second transaction have a shared address space within the memory, the memory having one or more memory partitions supporting one or more address spaces; in response to determining that the first transaction and the second transaction do not have the shared address space within the memory, assign the second transaction a second token of the first token type identical to the first token based on the transaction potential conflict check between the second transaction and the first transaction; and suppress detection of cache coherent conflicts in response to assigning the second transaction the second token identical to the first token such that cache coherency protocols are ignored, wherein suppressing detection of the cache coherent conflicts allows the first transaction to write to the cache line and the second transaction to write to the cache line concurrently. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A computer program product for assigning tokens to transactions in a transactional memory execution environment comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable storage medium does not comprise a transitory signal per se, wherein the computer readable program, when executed on a computing device, causes the computing device to:
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receive a first transaction having a first token of a first token type associated with the first transaction; receive a request for a transaction potential conflict check between the first transaction and a second transaction, wherein the first transaction is using a cache line; determine, in response to receiving the request for the transaction potential conflict check, whether the first transaction and the second transaction are conflicting, wherein determining whether the first transaction and the second transaction are conflicting includes at least determining whether the first transaction and the second transaction have a shared address space within a memory, the memory having one or more memory partitions supporting one or more address spaces; in response to determining that the first transaction and the second transaction do not have the shared address space within the memory, assign the second transaction a second token of the first token type identical to the first token based on the transaction potential conflict check between the second transaction and the first transaction; and suppress detection of cache coherent conflicts in response to assigning the second transaction the second token identical to the first token such that cache coherency protocols are ignored, wherein suppressing detection of the cache coherent conflicts allows the first transaction to write to the cache line and the second transaction to write to the cache line concurrently. - View Dependent Claims (14)
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15. A system for assigning tokens to transactions in a transactional memory environment, wherein a transaction is created by at least one thread, the system comprising:
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a memory; a processor device; and a system controller communicatively coupled to the processor device and the memory, wherein the system controller is configured to; receive a first transaction having a first token of a first token type associated with the first transaction; receive a request for a transaction potential conflict check between the first transaction and a second transaction, wherein the first transaction is using a cache line; determine, in response to receiving the request for the transaction potential conflict check, whether the first transaction and the second transaction are conflicting, wherein determining whether the first transaction and the second transaction are conflicting includes at least determining whether the first transaction and the second transaction have a shared address space within the memory, the memory having one or more memory partitions supporting one or more address spaces; in response to determining that the first transaction and the second transaction do not have the shared address space within the memory, assign the second transaction a second token of a second token type different from the first token type based on the transaction potential conflict check between the second transaction and the first transaction, wherein the second token type is compatible with the first token type, wherein the first token type includes a compatibility list of a set of token types of which the first token type is compatible; and suppress detection of cache coherent conflicts in response to assigning the second transaction the second token compatible with the first token such that cache coherency protocols are ignored, wherein suppressing detection of the cache coherent conflicts allows the first transaction to write to the cache line and the second transaction to write to the cache line concurrently.
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Specification