CMOS ultrasonic transducers and related apparatus and methods

• US 10,272,470 B2
• Filed: 04/28/2017
• Issued: 04/30/2019
• Est. Priority Date: 02/05/2013
• Status: Active Grant

• Current Assignee: BFLY Operations, Inc. (Butterfly Network, Inc.)
• Original Assignee: Butterfly Network, Inc.
• Inventors: Rothberg, Jonathan M., Fife, Keith G., Ralston, Tyler S., Charvat, Gregory L., Sanchez, Nevada J.
• Primary Examiner(s): Le, Thao X
• Assistant Examiner(s): Tynes, Jr., Lawrence C
• Application Number:
  US15/581,511
• Publication Number:
  US 20170225196A1
• Time in Patent Office: 732 Days
• Field of Search: 438 51
• CPC Class Codes: B06B 1/02 making use of electrical energy B06B1/18, B06B1/20 take precedence
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81B 3/0021 Transducers for transforming electrical into mechanical energy or vice versa dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81C 1/00158 Diaphragms, membranes manufacture process for semi-permeable inorganic membranes B01D67/0039
• CPC Class Codes: B81C 2201/013 Etching
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: G10K 11/18 Methods or devices for transmitting, conducting or directing sound G10K11/02, G10K11/36 take precedence
• CPC Class Codes: G10K 9/12 electrically operated

Abstract

CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

Claims

1. A method, comprising:

forming a cavity in a first wafer above an integrated circuit in the first wafer, wherein forming the cavity comprises etching an upper surface of the first wafer down to an etch stop layer of the first wafer;

directly bonding the first wafer and a second wafer to seal the cavity of the first wafer with the second wafer to form a sealed cavity, wherein the second wafer defines an SOI wafer including a buried insulator layer; and

forming an ultrasonic transducer membrane from the second wafer, wherein forming the ultrasonic transducer membrane from the second wafer comprises thinning a backside of the second wafer distal the cavity, and wherein thinning the backside of the second wafer comprises etching a base silicon layer of the second wafer until reaching the buried insulator layer.

2. The method of claim 1, wherein etching the base silicon layer further comprises using a selective etch for which the buried insulator layer functions as an etch stop layer of the second wafer.

3. The method of claim 1, wherein the buried insulator layer is SiO₂.

4. The method of claim 1, wherein the etch stop layer comprises a metal electrode structure of the first wafer.

5. The method of claim 1, further comprising forming a conductive layer on an insulating layer of the first wafer, wherein forming the cavity comprises etching the conductive layer to the insulating layer such that the insulating layer serves as the etch stop layer.

6. The method of claim 5, wherein the conductive layer is a doped silicon layer.

7. The method of claim 5, wherein the conductive layer is a metal layer.

8. The method of claim 1, wherein the bonding results in a silicon-to-silicon bond between the first and second wafers.

9. A method, comprising:

forming a cavity in a first wafer above an integrated circuit in the first wafer, wherein forming the cavity comprises etching an upper surface of the first wafer down to an etch stop layer of the first wafer;

directly bonding the first wafer and a second wafer to seal the cavity of the first wafer with the second wafer to form a sealed cavity, wherein the second wafer comprises a layer of polysilicon proximate the cavity of the first wafer, a layer of silicon, and an insulator between the layer of polysilicon and the layer of silicon; and

forming an ultrasonic transducer membrane from the second wafer, wherein forming the ultrasonic transducer membrane from the second wafer comprises thinning a backside of the second wafer distal the cavity, and wherein thinning the backside of the second wafer comprises etching the layer of silicon until reaching the insulator.

10. The method of claim 9, wherein etching the layer of silicon until the insulator is reached comprises using a selective etch for which the insulator functions as an etch stop layer of the etch stop layer.

11. The method of claim 10, wherein the insulator is SiO₂.

12. A method, comprising:

forming a cavity in a first wafer above an integrated circuit in the first wafer, wherein forming the cavity comprises etching an upper surface of the first wafer down to an etch stop layer of the first wafer;

directly bonding the first wafer and a second wafer to seal the cavity of the first wafer with the second wafer to form a sealed cavity, wherein the second wafer comprises a layer of amorphous silicon proximate the cavity of the first wafer, a layer of silicon, and an insulator between the layer of amorphous silicon and the layer of silicon; and

forming an ultrasonic transducer membrane from the second wafer, wherein forming the ultrasonic transducer membrane from the second wafer comprises thinning a backside of the second wafer distal the cavity, wherein thinning the backside of the second wafer comprises etching the layer of silicon until the insulator is reached.

13. The method of claim 12, wherein the insulator is SiO₂.

14. A method, comprising:

forming a cavity in a first wafer above an integrated circuit in the first wafer, wherein forming the cavity comprises etching an upper surface of the first wafer down to an etch stop layer of the first wafer;

directly bonding the first wafer and a second wafer to seal the cavity of the first wafer with the second wafer to form a sealed cavity; and

forming an ultrasonic transducer membrane from the second wafer,

further comprising forming an oxide layer on the etched first wafer prior to the bonding such that the bonding results in a silicon-to-oxide bond between the first and second wafers.