Methods and systems for managing data migration in solid state non-volatile memory
First Claim
1. A memory device, comprising:
- high endurance solid state memory having a first program-erase (P/E) cycle endurance level;
low endurance solid state memory having a second program-erase (P/E) cycle endurance level that is less than the first program-erase (P/E) cycle endurance level;
at least one programmable integrated circuit programmed to control writing of incoming data to the memory device by;
writing all incoming data to data blocks in the high endurance solid state memory,invalidating existing data in the data blocks of the low endurance solid state memory and the high endurance solid state memory corresponding to a logical block address (LBA) as it is modified by the LBA of the incoming data,determining a LBA update frequency of the valid data in the data blocks of the high endurance solid state memory,identifying valid high frequency LBA update data in the data blocks of the high endurance solid state memory that has a LBA update frequency that is greater than a LBA update frequency of other high frequency LBA update data in the data blocks of the high endurance solid state memory, andmigrating valid low frequency LBA update data to the data blocks of the low endurance solid state memory from data blocks of the high endurance solid state memory that also contain invalidated data, and not migrating any valid high frequency LBA update data from the data blocks of the high endurance solid state memory to the data blocks of the low endurance solid state memory.
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Abstract
Methods and systems that may be implemented for managing data migration from relatively higher performance and higher endurance solid state non-volatile memory media to relatively lower performance and lower endurance solid state non-volatile memory media. The disclosed methods and systems may be implemented to reduce write amplification that occurs to solid state non-volatile memory media of a memory device by using frequency of LBA update as a parameter for controlling and optimizing data eviction from a relatively higher performance and higher endurance input buffer section in the receiving front of a memory device to a relatively lower performance and lower endurance main memory section of the same memory device.
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Citations
20 Claims
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1. A memory device, comprising:
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high endurance solid state memory having a first program-erase (P/E) cycle endurance level; low endurance solid state memory having a second program-erase (P/E) cycle endurance level that is less than the first program-erase (P/E) cycle endurance level; at least one programmable integrated circuit programmed to control writing of incoming data to the memory device by; writing all incoming data to data blocks in the high endurance solid state memory, invalidating existing data in the data blocks of the low endurance solid state memory and the high endurance solid state memory corresponding to a logical block address (LBA) as it is modified by the LBA of the incoming data, determining a LBA update frequency of the valid data in the data blocks of the high endurance solid state memory, identifying valid high frequency LBA update data in the data blocks of the high endurance solid state memory that has a LBA update frequency that is greater than a LBA update frequency of other high frequency LBA update data in the data blocks of the high endurance solid state memory, and migrating valid low frequency LBA update data to the data blocks of the low endurance solid state memory from data blocks of the high endurance solid state memory that also contain invalidated data, and not migrating any valid high frequency LBA update data from the data blocks of the high endurance solid state memory to the data blocks of the low endurance solid state memory. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An information handling system, comprising:
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a host programmable integrated circuit; a memory device coupled to receive incoming data from the host programmable integrated circuit, the memory device comprising; high endurance solid state memory having a first program-erase (P/E) cycle endurance level, low endurance solid state memory having a second program-erase (P/E) cycle endurance level that is less than the first program-erase (P/E) cycle endurance level, and at least one programmable integrated circuit; where the at least one programmable integrated circuit of the memory device is programmed to control writing of incoming data to the memory device by; writing all the incoming data to data blocks in the high endurance solid state memory, invalidating existing data in the data blocks of the low endurance solid state memory and the high endurance solid state memory corresponding to a logical block address (LBA) as it is modified by the LBA of the incoming data, determining a LBA update frequency of valid data in the data blocks of the high endurance solid state memory, identifying valid high frequency LBA update data in the data blocks of the high endurance solid state memory that has a LBA update frequency that is greater than a LBA update frequency of other high frequency LBA update data in the data blocks of the high endurance solid state memory, and migrating valid low frequency LBA update data to the data blocks of the low endurance solid state memory from data blocks of the high endurance solid state memory that also contain invalidated data, and not migrating any valid high frequency LBA update data from the data blocks of the high endurance solid state memory to the data blocks of the low endurance solid state memory. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method of operating a memory device comprising:
receiving incoming data in a memory device from a host programmable integrated circuit, the memory device comprising; high endurance solid state memory having a first program-erase (P/E) cycle endurance level, and low endurance solid state memory having a second program-erase (P/E) cycle endurance level that is less than the first program-erase (P/E) cycle endurance level; and controlling writing of the incoming data to the memory device by; writing all the incoming data to data blocks in the high endurance solid state memory, invalidating existing data in the data blocks of the low endurance solid state memory and the high endurance solid state memory corresponding to a logical block address (LBA) as it is modified by the LBA of the incoming data, determining a LBA update frequency of the valid data in the data blocks of the high endurance solid state memory, identifying valid high frequency LBA update data in the data blocks of the high endurance solid state memory that has a LBA update frequency that is greater than a LBA update frequency of other high frequency LBA update data in the data blocks of the high endurance solid state memory, and migrating valid low frequency LBA update data to the data blocks of the low endurance solid state memory from data blocks of the high endurance solid state memory that also contain invalidated data, and not migrating any valid high frequency LBA update data from the data blocks of the high endurance solid state memory to the data blocks of the low endurance solid state memory. - View Dependent Claims (15, 16, 17, 18, 19, 20)
Specification