Reserving a core of a processor complex for a critical task

• US 10,275,280 B2
• Filed: 08/10/2016
• Issued: 04/30/2019
• Est. Priority Date: 08/10/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Borlick, Matthew G., Gupta, Lokesh M., Hardy, Clint A., Nguyen, Trung N.
• Primary Examiner(s): Ghaffari, Abu
• Application Number:
  US15/233,295
• Publication Number:
  US 20180046507A1
• Time in Patent Office: 993 Days
• Field of Search: None
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/4887 involving deadlines, e.g. rate based, periodic
• CPC Class Codes: G06F 9/5038 considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration scheduling strategies G06F9/4881 and subgroups
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06F 9/5066 Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs mappping at compile time, see G06F8/451

Abstract

A plurality of cores are maintained in a processor complex. A core of the plurality of cores is reserved for execution of critical tasks, wherein it is preferable to prioritize execution of critical tasks over non-critical tasks. A scheduler receives a task for scheduling in the plurality of cores. In response to determining that the task is a critical task, the task is scheduled for execution in the reserved core.

Claims

1. A method, comprising:

reserving a single core of a plurality of cores of a processor complex for execution of critical tasks, wherein execution of critical tasks is prioritized over execution of non-critical tasks, wherein no more cores other than the single core is reserved for the execution of critical tasks, and wherein the single core comprises fewer than 5% of a total number of the plurality of cores of the processor complex;

receiving, by a scheduler, a task for scheduling in the plurality of cores;

in response to determining that the task is a critical task, scheduling the task for execution in the reserved core, wherein the reserved core has a clean L1 cache and a clean L2 cache at a time at which the critical task is scheduled for execution in the reserved core and no other tasks besides the critical task are running on the reserved core at the time;

in response to the critical task being scheduled on the reserved core, the critical task secures exclusive access to the L1 cache and the L2 cache of the reserved core and executes a timeslice of the critical task on the reserved core, wherein if data is not found in the L1 cache of the reserved core then the data is retrieved from the L2 cache of the reserved core, and wherein each core of the plurality of cores have different sets of L1 cache and L2 cache but share a L3 cache; and

in response to completion of the timeslice of the critical task, the scheduler schedules no task except for critical tasks on the reserved core.

2. The method of claim 1, the method further comprising:

in response to determining that the task is a non-critical task, scheduling the task for execution in a non-reserved core of the plurality of cores.

3. The method of claim 2, wherein the critical task executes faster by using the L1 cache and the L2 cache of the reserved core, in comparison to scheduling the critical task on any non-reserved core of the plurality of cores, wherein in non-reserved cores L1 and L2 cache are shared among a plurality of tasks.

4. The method of claim 2, wherein:

the reserved core is not running any task, at a time at which the critical task secures exclusive access to the L1 cache and the L2 cache of the reserved core to start executing the timeslice of the critical task on the reserved core; and

the L1 cache and the L2 cache do not have any data that needs to be retained at a time at which the timeslice of the critical task starts executing on the reserved core.

5. The method of claim 2, wherein the critical task is a task that indicates completion of stage and destage requests with respect to a cache of the processor complex.

6. The method of claim 1, wherein the plurality of cores are included in a plurality of chips of the processor complex, and wherein at least two processor complexes are included in a dual-server based storage system in which the processor complex is substituted by another processor complex in response to a failure of the processor complex.

7. A system, comprising:

a memory; and

a processor coupled to the memory, wherein the processor performs operations, the operations comprising;

reserving a single core of a plurality of cores of a processor complex for execution of critical tasks, wherein execution of critical tasks is prioritized over execution of non-critical tasks, wherein no more cores other than the single core is reserved for the execution of critical tasks, and wherein the single core comprises fewer than 5% of a total number of the plurality of cores of the processor complex;

receiving, by a scheduler, a task for scheduling in the plurality of cores;

in response to determining that the task is a critical task, scheduling the task for execution in the reserved core, wherein the reserved core has a clean L1 cache and a clean L2 cache at a time at which the critical task is scheduled for execution in the reserved core and no other tasks besides the critical task are running on the reserved core at the time;

in response to the critical task being scheduled on the reserved core, the critical task secures exclusive access to the L1 cache and the L2 cache of the reserved core and executes a timeslice of the critical task on the reserved core, wherein if data is not found in the L1 cache of the reserved core then the data is retrieved from the L2 cache of the reserved core, and wherein each core of the plurality of cores have different sets of L1 cache and L2 cache but share a L3 cache; and

in response to completion of the timeslice of the critical task, the scheduler schedules no task except for critical tasks on the reserved core.

8. The system of claim 7, the operations further comprising:

in response to determining that the task is a non-critical task, scheduling the task for execution in a non-reserved core of the plurality of cores.

9. The system of claim 8, wherein the critical task executes faster by using the L1 cache and the L2 cache of the reserved core, in comparison to scheduling the critical task on any non-reserved core of the plurality of cores, wherein in non-reserved cores L1 and L2 cache are shared among a plurality of tasks.

10. The system of claim 8, wherein:

the reserved core is not running any task, at a time at which the critical task secures exclusive access to the L1 cache and the L2 cache of the reserved core to start executing the timeslice of the critical task on the reserved core; and

the L1 cache and the L2 cache do not have any data that needs to be retained at a time at which the timeslice of the critical task starts executing on the reserved core.

11. The system of claim 8, wherein the critical task is a task that indicates completion of stage and destage requests with respect to a cache of the processor complex.

12. The system of claim 7, wherein the plurality of cores are included in a plurality of chips of the processor complex, and wherein at least two processor complexes are included in a dual-server based storage system in which the processor complex is substituted by another processor complex in response to a failure of the processor complex.

13. A computer program product, the computer program product comprising a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code configured to perform operations, the operations comprising:

reserving a single core of a plurality of cores of a processor complex for execution of critical tasks, wherein execution of critical tasks is prioritized over execution of non-critical tasks, wherein no more cores other than the single core is reserved for the execution of critical tasks, and wherein the single core comprises fewer than 5% of a total number of the plurality of cores of the processor complex;

receiving, by a scheduler, a task for scheduling in the plurality of cores;

in response to determining that the task is a critical task, scheduling the task for execution in the reserved core, wherein the reserved core has a clean L1 cache and a clean L2 cache at a time at which the critical task is scheduled for execution in the reserved core and no other tasks besides the critical task are running on the reserved core at the time;

in response to the critical task being scheduled on the reserved core, the critical task secures exclusive access to the L1 cache and the L2 cache of the reserved core and executes a timeslice of the critical task on the reserved core, wherein if data is not found in the L1 cache of the reserved core then the data is retrieved from the L2 cache of the reserved core, and wherein each core of the plurality of cores have different sets of L1 cache and L2 cache but share a L3 cache; and

in response to completion of the timeslice of the critical task, the scheduler schedules no task except for critical tasks on the reserved core.

14. The computer program product of claim 13, the operations further comprising:

in response to determining that the task is a non-critical task, scheduling the task for execution in a non-reserved core of the plurality of cores.

15. The computer program product of claim 14, wherein:

the reserved core is not running any task, at a time at which the critical task secures exclusive access to the L1 cache and the L2 cache of the reserved core to start executing the timeslice of the critical task on the reserved core; and

the L1 cache and the L2 cache do not have any data that needs to be retained at a time at which the timeslice of the critical task starts executing on the reserved core.

16. The computer program product of claim 14, wherein the critical task is a task that indicates completion of stage and destage requests with respect to a cache of the processor complex.

17. The computer program product of claim 13, wherein the plurality of cores are included in a plurality of chips of the processor complex, and wherein at least two processor complexes are included in a dual-server based storage system in which the processor complex is substituted by another processor complex in response to a failure of the processor complex.

18. A storage system, comprising:

a first server; and

a second server coupled to the first server, wherein the storage system is configurable to perform operations, the operations comprising;

reserving a single core of a plurality of cores of a processor complex for execution of critical tasks, wherein execution of critical tasks is prioritized over execution of non-critical tasks, wherein no more cores other than the single core is reserved for the execution of critical tasks, and wherein the single core comprises fewer than 5% of a total number of the plurality of cores of the processor complex;

receiving, by a scheduler, a task for scheduling in the plurality of cores;

in response to determining that the task is a critical task, scheduling the task for execution in the reserved core, wherein the reserved core has a clean L1 cache and a clean L2 cache at a time at which the critical task is scheduled for execution in the reserved core and no other tasks besides the critical task are running on the reserved core at the time;

in response to the critical task being scheduled on the reserved core, the critical task secures exclusive access to the L1 cache and the L2 cache of the reserved core and executes a timeslice of the critical task on the reserved core, wherein if data is not found in the L1 cache of the reserved core then the data is retrieved from the L2 cache of the reserved core, and wherein each core of the plurality of cores have different sets of L1 cache and L2 cache but share a L3 cache; and

in response to completion of the timeslice of the critical task, the scheduler schedules no task except for critical tasks on the reserved core.

19. The storage system of claim 18, the operations further comprising:

in response to determining that the task is a non-critical task, scheduling the task for execution in a non-reserved core of the plurality of cores.

20. The storage system of claim 19, wherein:

the reserved core is not running any task, at a time at which the critical task secures exclusive access to the L1 cache and the L2 cache of the reserved core to start executing the timeslice of the critical task on the reserved core; and

the L1 cache and the L2 cache do not have any data that needs to be retained at a time at which the timeslice of the critical task starts executing on the reserved core.

21. The storage system of claim 19, wherein the critical task is a task that indicates completion of stage and destage requests with respect to a cache of the processor complex.

22. A server computational device of a dual-server storage system, the server computational device comprising:

memory; and

a processor coupled to the memory, wherein the processor performs operations, the operations comprising;

reserving a single core of a plurality of cores of a processor complex for execution of critical tasks, wherein execution of critical tasks is prioritized over execution of non-critical tasks, wherein no more cores other than the single core is reserved for the execution of critical tasks, and wherein the single core comprises fewer than 5% of a total number of the plurality of cores of the processor complex;

receiving, by a scheduler, a task for scheduling in the plurality of cores;

in response to determining that the task is a critical task, scheduling the task for execution in the reserved core, wherein the reserved core has a clean L1 cache and a clean L2 cache at a time at which the critical task is scheduled for execution in the reserved core and no other tasks besides the critical task are running on the reserved core at the time;

in response to the critical task being scheduled on the reserved core, the critical task secures exclusive access to the L1 cache and the L2 cache of the reserved core and executes a timeslice of the critical task on the reserved core, wherein if data is not found in the L1 cache of the reserved core then the data is retrieved from the L2 cache of the reserved core, and wherein each core of the plurality of cores have different sets of L1 cache and L2 cache but share a L3 cache; and

in response to completion of the timeslice of the critical task, the scheduler schedules no task except for critical tasks on the reserved core.

23. The server computational device of claim 22, the operations further comprising:

in response to determining that the task is a non-critical task, scheduling the task for execution in a non-reserved core of the plurality of cores.

24. The server computational device of claim 23, wherein:

the reserved core is not running any task, at a time at which the critical task secures exclusive access to the L1 cache and the L2 cache of the reserved core to start executing the timeslice of the critical task on the reserved core; and

the L1 cache and the L2 cache do not have any data that needs to be retained at a time at which the timeslice of the critical task starts executing on the reserved core.

25. The server computational device of claim 23, wherein the critical task is a task that indicates completion of stage and destage requests with respect to a cache of the processor complex.