Dynamic boot image streaming
First Claim
Patent Images
1. A method comprising:
- executing, from a first memory of a host device, a data transfer command to stream, via a direct memory access (DMA) controller, a header stored in the first memory to a base address of a second memory of the host device;
executing a data link command to stall the DMA controller for at least a portion of time during which a processor of the host device constructs, based on the header streamed to the second memory, additional data transfer commands in the second memory for streaming, via the DMA controller, multiple boot images stored in the first memory to non-contiguous locations of the second memory or to a third memory of the host device; and
in response to the data link command being pointed to a first data transfer command of the additional data transfer commands, causing the DMA controller to resume effective to stream, via the DMA controller and based at least in part on the first data transfer command, the multiple boot images from the first memory to the non-contiguous locations of the second memory or to the third memory of the host device.
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Abstract
The present disclosure describes apparatuses and techniques for dynamic boot image streaming. In some aspects a memory controller that is streaming multiple boot images from a first memory to a second memory is stalled, a descriptor for streaming one of the multiple boot images from the first memory to a non-contiguous memory location is generated while the memory controller is stalled, and the memory controller is resumed effective to cause the memory controller to stream, based on the descriptor generated while the memory controller is stalled, the second boot image to the non-contiguous memory location.
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Citations
20 Claims
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1. A method comprising:
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executing, from a first memory of a host device, a data transfer command to stream, via a direct memory access (DMA) controller, a header stored in the first memory to a base address of a second memory of the host device; executing a data link command to stall the DMA controller for at least a portion of time during which a processor of the host device constructs, based on the header streamed to the second memory, additional data transfer commands in the second memory for streaming, via the DMA controller, multiple boot images stored in the first memory to non-contiguous locations of the second memory or to a third memory of the host device; and in response to the data link command being pointed to a first data transfer command of the additional data transfer commands, causing the DMA controller to resume effective to stream, via the DMA controller and based at least in part on the first data transfer command, the multiple boot images from the first memory to the non-contiguous locations of the second memory or to the third memory of the host device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory device comprising:
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a memory controller configured to provide an interface to a data bus of a host device; a direct memory access (DMA) controller configured to stream data of the memory device to other memory devices of the host device via the data bus; and memory storage media configured to store the data of the memory device, the data of the memory device comprising; multiple boot images executable by a processor of the host device to initialize components of the host device; a header executable by the processor of the host device to construct a series of data transfer commands for streaming the multiple boot images, via the DMA controller, to non-contiguous locations of the other memory devices; another data transfer command associated with the header that, when executed by the memory controller, streams the header, via the DMA controller, to one of the other memory devices of the host device; and a data link command that; (i) when executed by the memory controller, stalls the DMA controller effective to permit the header to be executed from the other memory device by the processor to construct the series of data transfer commands for streaming, via the DMA controller, the multiple boot images, and (ii) when pointed to a first data transfer command of the series of data transfer commands, causes the DMA controller to resume operation effective to stream, via the DMA controller and based at least in part on the first data transfer command, the multiple boot images to the non-contiguous locations of the other memory devices. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. An apparatus comprising:
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a processor configured to execute processor-executable instructions; a memory from which processor-executable instructions are executable by the processor; and an embedded memory device comprising; a memory controller having an interface to a data bus of the apparatus; a direct memory access (DMA) controller configured to stream data of the embedded memory device to the memory of the apparatus via the data bus; and memory storage media storing the data of the embedded memory device, the data of the embedded memory device comprising; multiple boot images executable by the processor to initialize components of the apparatus; a header executable by the processor to construct a series of data transfer commands for streaming the multiple boot images, via the DMA controller, to non-contiguous locations of the memory of the apparatus; another data transfer command associated with the header that, when executed by the memory controller, streams the header, via the DMA controller, to the memory of the apparatus; and a data link command that; (i) when executed by the memory controller, stalls the DMA controller effective to permit the header to be executed from the memory of the apparatus by the processor to construct the series of data transfer commands for streaming, via the DMA controller, the multiple boot images; and (ii) when pointed to a first data transfer command of the series of data transfer commands, causes the DMA controller to resume operation effective to stream, based at least in part on the first data transfer command, the multiple boot images to the non-contiguous locations of the memory of the apparatus. - View Dependent Claims (19, 20)
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Specification