Unit shift register circuit, shift register circuit, control method for unit shift register circuit, and display device

• US 10,276,122 B2
• Filed: 10/23/2015
• Issued: 04/30/2019
• Est. Priority Date: 10/28/2014
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Yamamoto, Kaoru, Ogawa, Yasuyuki
• Primary Examiner(s): Lam, Tuan T
• Application Number:
  US15/522,425
• Publication Number:
  US 20170323612A1
• Time in Patent Office: 1,285 Days
• Field of Search: None
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0871 with level shifting
• CPC Class Codes: G09G 2310/0208 using active addressing
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

In a forward shift operation, a second input signal having a higher voltage than a voltage of a first input signal is input to a second gate terminal in a case that a first gate terminal of a first transistor is charged, and a fourth input signal having a higher voltage than a voltage of a third input signal is input to a third gate terminal in a case that the first gate terminal of the first transistor is discharged. In a backward shift operation, the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is charged, and the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is discharged.

Claims

1. A unit shift register circuit constituting each stage of a shift register circuit, the unit shift register circuit comprising:

a first transistor that includes a first gate terminal, a first source terminal, and a first drain terminal, receives a first clock signal to the first drain terminal, and outputs an output signal from the first source terminal;

a second transistor that includes a second gate terminal, a second source terminal, and a second drain terminal, the second source terminal being connected to the first gate terminal of the first transistor, receives a first input signal to the second drain terminal, and inputs a second input signal to the second gate terminal; and

a third transistor that includes a third gate terminal, a third source terminal, and a third drain terminal, the third source terminal being connected to the first gate terminal of the first transistor, receives a third input signal to the third drain terminal, and inputs a fourth input signal to the third gate terminal,

wherein, in a forward shift operation, the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is charged, and the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is discharged, and

wherein, in a backward shift operation, the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is charged, and the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is discharged.

2. The unit shift register circuit according to claim 1,

wherein the first input signal is an output signal of the unit shift register circuit at a preceding stage of the unit shift register circuit,

wherein the second input signal is a signal of the first gate terminal of the first transistor of the unit shift register circuit of the stage before the preceding stage of the unit shift register circuit,

wherein the third input signal is an output signal of the unit shift register circuit at a subsequent stage of the unit shift register circuit, and

wherein the fourth input signal is a signal of the first gate terminal of the first transistor of the unit shift register circuit of the stage after the subsequent stage of the unit shift register circuit.

3. The unit shift register circuit according to claim 1,

wherein the first input signal is a clock signal whose cycle deviates backward from the first clock signal by ¼

of a cycle in a forward shift operation and whose cycle deviates forward from the first clock signal by ¼

of a cycle in a backward shift operation,

wherein the second input signal is a signal of the first gate terminal of the first transistor of the unit shift register circuit of the stage before the preceding stage of the unit shift register circuit,

wherein the third input signal is a clock signal whose cycle deviates forward from the first clock signal by ¼

of a cycle in a forward shift operation and whose cycle deviates backward from the first clock signal by ¼

of a cycle in a backward shift operation, and

wherein the fourth input signal is a signal of the first gate terminal of the first transistor of the unit shift register circuit of the stage after the subsequent stage of the unit shift register circuit.

4. The unit shift register circuit according to claim 1,

wherein, in the forward shift operation, in a case that the second transistor charges the first gate terminal of the first transistor, the first input signal and the second input signal rise, and after the first gate terminal is charged, a voltage of the second input signal falls earlier than a fall of a voltage of the first input signal, and

wherein, in the backward shift operation, in a case that the third transistor charges the first gate terminal of the first transistor, the third input signal and the fourth input signal rise, and after the first gate terminal is charged, a voltage of the fourth input signal falls earlier than a fall of a voltage of the third input signal.

5. The unit shift register circuit according to claim 1,

wherein the first transistor boosts the output signal through a bootstrap operation of boosting a voltage of the first gate terminal using a voltage charged in a parasitic capacitance between the first source terminal and the first gate terminal.

6. The unit shift register circuit according to claim 1,

wherein, in the forward shift operation, in a case that the third transistor discharges the first gate terminal of the first transistor, the third input signal and the fourth input signal rise, and after the first gate terminal is discharged, a voltage of the third input signal falls earlier than a fall of a voltage of the fourth input signal, and

wherein, in the backward shift operation, in a case that the second transistor discharges the first gate terminal of the first transistor, the first input signal and the second input signal rise, and after the first gate terminal is discharged, a voltage of the first input signal falls earlier than a fall of a voltage of the second input signal.

7. The unit shift register circuit according to claim 1, further comprising:

a capacitive element connected between the first gate terminal and the first source terminal of the first transistor.

8. The unit shift register circuit according to claim 1, further comprising:

a pull-down circuit that pulls down the output signal of the first source terminal in accordance with a second clock signal having an opposite phase to the first clock signal.

9. The unit shift register circuit according to claim 1, further comprising:

a fifth transistor that connects the first gate terminal and the first source terminal of the first transistor in accordance with the first clock signal.

10. The unit shift register circuit according to claim 1, further comprising:

a pull-down circuit that pulls down the first gate terminal of the first transistor in accordance with a voltage of the first gate terminal.

11. The unit shift register circuit according to claim 10,

wherein the pull-down circuit includes an inverter circuit that includes the first gate terminal as an input and a fifth transistor of which a gate receives input of the output of the inverter circuit and a drain terminal is connected to the first gate terminal, and pulls down the first gate terminal in accordance with a voltage of the first gate terminal.

12. The unit shift register circuit according to claim 1, further comprising:

a pull-down circuit that pulls down the first gate terminal of the first transistor in accordance with a second clock signal having an opposite phase to the first clock signal and a voltage of the first gate terminal.

13. The unit shift register circuit according to claim 12,

wherein the pull-down circuit includes a push-pull circuit for the first clock signal and the second clock signal having an opposite phase, a seventh transistor of which a gate terminal receives input of the first gate terminal that pulls down an output node of the push-pull circuit, and a fifth transistor of which a gate receives input of the output node of the push-pull circuit and a drain terminal is connected to the first gate terminal, and the first gate terminal is pulled down in accordance with a voltage of the first gate terminal.

14. The unit shift register circuit according to claim 1, further comprising:

a fifth transistor that is connected to the second transistor in parallel, of which a gate receives input of a clock signal of which a cycle deviates backward from the first clock signal by ¼

of a cycle in the forward shift operation and a cycle deviates forward from the first clock signal by ¼

of a cycle in the backward shift operation; and

a sixth transistor that is connected to the third transistor in parallel, of which a gate receives input of a clock signal of which a cycle deviates forward from the first clock signal by ¼

of a cycle in the forward shift operation and a cycle deviates backward from the first clock signal by ¼

of a cycle in the backward shift operation.

15. The unit shift register circuit according to claim 1, further comprising:

a pull-down circuit that pulls down the output signal of the first source terminal and the first gate terminal of the first transistor in accordance with a predetermined clear signal.

16. The unit shift register circuit according to claim 1,

wherein the second transistor and the third transistor connected to the first gate terminal of the first transistor are constituted by a plurality of transistors in cascade connection.

17. The unit shift register circuit according to claim 16, further comprising:

a pull-down circuit that pulls down the output signal of the first source terminal in accordance with a second clock signal having an opposite phase to the first clock signal.

18. The unit shift register circuit according to claim 1,

wherein at least the first transistor, the second transistor, and the third transistor include an oxide semiconductor in a semiconductor layer.

19. A control method for a unit shift register circuit that constitutes each stage of a shift register circuit,

wherein the unit shift register circuit includes:

a first transistor that includes a first gate terminal, a first source terminal, and a first drain terminal, receives a clock signal to the first drain terminal, and outputs an output signal from the first source terminal;

a second transistor that includes a second gate terminal, a second source terminal, and a second drain terminal, the second source terminal being connected to the first gate terminal of the first transistor, receives a first input signal to the second drain terminal, and inputs a second input signal to the second gate terminal; and

a third transistor that includes a third gate terminal, a third source terminal, and a third drain terminal, the third source terminal being connected to the first gate terminal of the first transistor, receives a third input signal to the third drain terminal, and inputs a fourth input signal to the third gate terminal,

wherein, in a forward shift operation, the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is charged, and the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is discharged, and

wherein, in a backward shift operation, the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is charged, and the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is discharged.

20. A display device comprising:

a plurality of pixels;

a plurality of scanning lines to which the plurality of pixels are connected; and

a plurality of unit shift register circuits respectively constituting stages of a shift register circuit, wherein each of the plurality of unit shift register circuits includes;

a first transistor that includes a first gate terminal, a first source terminal, and a first drain terminal, receives a clock signal to the first drain terminal, and outputs an output signal from the first source terminal;

a second transistor that includes a second gate terminal, a second source terminal, and a second drain terminal, the second source terminal being connected to the first gate terminal of the first transistor, receives a first input signal to the second drain terminal, and inputs a second input signal to the second gate terminal; and

a third transistor that includes a third gate terminal, a third source terminal, and a third drain terminal, the third source terminal being connected to the first gate terminal of the first transistor, receives a third input signal to the third drain terminal, and inputs a fourth input signal to the third gate terminal, wherein, in a forward shift operation, the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is charged, and the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is discharged, and wherein, in a backward shift operation, the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is charged, and the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is discharged.